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Encounter to Virtuoso

October 31, 2013, 10:49 am
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 Hi all,

 It is my first time on this forum so please may apologize  my lack of knowledge in some matter.

I'll put my problem in context:

We are designing a mixed-signal project in technology tsmc65nm. I work on the digital side and I have problems to port my design in virtuoso. Right now, I have generate a digital circuit for my college in order to integrate it in his analog design in Virtuoso.

I succeed in creating the «gds» file and somehow importing it to Virtuoso but once I open it, the layer doesn't match and I have a bunch of DRC violations.

Then  I create a library and I imported the «lef» file of my standard cell (which also include layer etc) and I attach it to the technology file corresponding (*.tf). Then I created a «.def» file and I import it to this new library. In this way, I was able to see the good layer but no layout view of the standard. I tried some trick to get them but with no success...

I saw that it would be possible to translate «lef» file to oa library and then the transfert between Encounter and Virtuoso is much easier. But I tried but I think that I'm mixed up with all the required file.

 I can tell you the type of file that I have:

.lef => with the layer, standard cell etc

.map

.tf

If someone know a way I could solve my problem either by creating the OA lib of telling me the way to be able to transfert my design to Virtuoso and be able to see it with the standard cell layout and then pass the DRC, I would be more than happy.

If I misunderstanding some matter, feel free to educate me!

 Thank for your support

 

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Difference between net and hNets in db commands

November 26, 2013, 10:31 pm
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Hi,

A) What is the difference between the below two statements

1. set a1 [dbGet top.nets.name]
2. set a2 [dbGet top.hInst.hnets.name]

 B) Both 3 and 4 statements priniting the same name (RVXG1), which is the top module. Then how is the second statement helpful

3.dbGet top.name

4.dbGet top.hInst.cell.name 

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Multi point CTS implementation

November 28, 2013, 11:17 pm
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I have a netlist and def with single clock port clk.

I want to implement multi point cts with 4 clocks(clk1,clk2,clk3,clk4).They are equilent to clock port clk.

What are the flow steps in encounter to  implement this multipoint CTS.

(How can create 4 new clock ports and remove old clock port clk, how to take care of clock connectivity in the design and implementation of multi point CTS)

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LVS Issue with power

November 29, 2013, 12:36 am
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I have got one issue in LVS 

In my design i have preplaced cell named PowerClamp 4 in number, each cell has different instance name, it has common pin name "VDDESD" "VSSESD" 
pin "VDDESD" connect to power net named VDD0P9 for two cells and other two cell connect to different power domain named VDD1P8

Now issue is, In layout they are seen as different power net due to different instance name but in source (spice file ) they look by cell type one pin has two power net and report as short.
layout is fine, we need to inform tool these are different nets in spice file, i understood the problem but couldn't reach the solution to resolve this.
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uni-directional routing with EDI

December 2, 2013, 2:46 am
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Hi all, 

I am wondering how to force EDI router to strictly use the uni-directional routing only?

 Although the routing directions are already defined in the LEF file, the router still create jogs, staircase line... I looked though the manuals (EDI, nanoroute...), but cannot figure it out. 

I am very appreciated if anyone could help me. Thanks a lot. 

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error in qrc tech file

December 2, 2013, 5:01 am
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 Hi All ,

when  I am running qrc in stand alone mode  , I am seeing following error

ERROR (EXTSNZTECH-104) : The technology file defines layer active but does not specify the
resistance of that layer.

As the active layer is a base layer , I  Just want to continue to complete extraction by ignoring this error.

what are the switches that i need  to enable to ignore this error and proceed for extraction?.

 

Thanks in Advance.

 

 

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EndOfLine Violations

December 2, 2013, 6:27 am
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Hi,

   I am working with a set of standard cells that I created myself and am in the process of testing them. When I run verifyGeometry I get EndOf Line violations. A sample is pasted below:

EndOfLine: Blockage of Cell core/FE_OFC1095_OP2_0_ & Blockage of Cell core/rf/g34830  ( M1 )
Bounds : ( 196.355, 476.000 ) ( 196.455, 476.030 )
Actual:     0.1     Min:     0.11     Type: End Of Line

EndOfLine: Pin of Cell core/fetch/g1204 & Blockage of Cell core/fetch/g1204  ( M1 )
Bounds : ( 273.145, 522.600 ) ( 273.165, 522.700 )
Actual:     0.1     Min:     0.11     Type: End Of Line ParallelEdge 

These violations are always pin-to blockage or blockage-to-blockage. I realize that the source of the violations lies in the cells of my library, but would like to understand why these violations occur and how I can get rid of them. I have a feeling that generating the blockages correctly in the LEF would accomplish this and would like to get more information on that as well.

 Just to be clear, all the cells that I created have at least a half-pitch spacing between the pin(or the net on which the pin lies) and cell boundary. The violation messages seem to indicate that the actual violation is about 0.01µ or thereabouts. Is there a way to generate the blockages correctly so that these violations do not occur?

 

Any help is appreciated.

Thanks and regards,

Kasyab 

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trialRoute, error adjacent routing layers with same direction

December 3, 2013, 5:04 am
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 Hi there,

i am using Encounter 13.1 and a STM 28FDSOI kit. Floorplanning and prePlace of the design run smoothly but when I try a timeDesign, trialrout exits with the following error:

**ERROR: (ENCTR-7108):  Two adjacent routing layers M8 and M9 are in the same preferred direction.
trialRoute does not support this design style and will exit.

 

Where is this problem located ? Is it a LEF isssue, do I need to add another lef file? 

 Kind regards

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clockRouting, selectNet -allDefClock cannot find any clock

December 5, 2013, 2:20 am
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Hi there,

 as the subject says,

 selectNet -allDefCloc

is not able to find any clock nets:

 " **WARN: (ENCSYC-1188):  Cannot select clock net - could not find it."

 Although, I ran CTS in advance:

  ckSynthesis -forceReconvergent -rguide par_$Utilisation/ctgen/$Entity.guide -report par_$Utilisation/reports/$Entity.ctsrpt
  createClockTreeSpec -output par_$Utilisation/$Entity.ctstch\  -bufferList $CT_BUFFER
  specifyClockTree -file par_$Utilisation/$Entity.ctstch

  createSaveDir par_$Utilisation/ctgen
  ckSynthesis -forceReconvergent -rguide par_$Utilisation/ctgen/$Entity.guide -report par_$Utilisation/reports/$Entity.ctsrpt
  saveClockNets -output par_$Utilisation/ctgen/$Entity.ctsntf
  saveNetlist par_$Utilisation/ctgen/$Entity.v
  savePlace par_$Utilisation/ctgen/$Entity.place

 

I would be glad about any hints what to do.


Cheers,

Marten

 

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Encounter cannot find a valid clock net / Timing library is not loaded

December 12, 2013, 8:09 am
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In SoC encounter 11.0, after I execute the following command:
 
createClockTreeSpec -output ../CTS/${DESIGN_NAME}_spec.cts \
   -bufferList BUFX2 BUFX4 INVX1 INVX2 INVX4 INVX8
 
 
It gives me the following message: 
 
CTS treats D-pins and I/O pins as non-synchronous pins by default.
If you want to change the behavior, you need to use the SetDPinAsSync
or SetIoPinAsSync statement in the clock tree specification file,
or use the setCTSMode -traceDPinAsLeaf {true|false} command,
or use the setCTSMode -traceIoPinAsLeaf {true|false} command
before specifyClockTree command.

*** End specifyClockTree (cpu=0:00:00.0, real=0:00:00.0, mem=345.0M) ***
<clockDesign CMD> ckSynthesis -report ../RPT/SboxWrapper/clock.report -forceReconvergent -breakLoop
Checking spec file integrity...
**WARN: (ENCCK-178):    CTS cannot find a valid clock net.
**WARN: (ENCCK-313):    You have not specified a clock tree. Use the specifyClockTree command to do so.
*** End ckSynthesis (cpu=0:00:00.0, real=0:00:00.0, mem=345.0M) ***
**clockDesign ... cpu = 0:00:00, real = 0:00:00, mem = 345.0M **
<CMD> optDesign -postCTS -hold -outDir ../RPT/SboxWrapper
**DIAG[opUtil.c:10662:update]: Assert "powerView != tocDefaultView"
**DIAG[opUtil.c:10667:update]: Assert "powerViewTlc"
**DIAG[opUtil.c:10662:update]: Assert "powerView != tocDefaultView"
**DIAG[opUtil.c:10667:update]: Assert "powerViewTlc"
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 345.2M, totSessionCpu=0:00:05 **
**ERROR: (ENCOPT-6029): Timing Library is not loaded yet**ERROR: (ENCSYT-6692): [SoC_Encounter.tcl]: Invalid return code while executing "SoC_Encounter.tcl"
 
 
What could be the reason for this? My design does have a clock. 
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How to skip ERROR in cadence encounter13.2

November 7, 2013, 1:18 am
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Hi All,

When i am source eco file i am getting ERROR.so its stop due to ERROR occur.

so is there  any command available in encounter so we can skipp ERROR and run full file without stop anywhere??

means whenever  ERROR come then it should skipp and executenext command of that eco file.

 

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verifyconnectivity

July 11, 2013, 9:14 pm
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After doing the verify connectivity, I am getting the error "dangling wires" . Please guide me how to solve the problem

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rc extraction in encounter

May 14, 2013, 7:30 am
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Hi,

 I'm using encounter for a tape-out. I want to use QRC for higher accuracy. However, I think I need to tell the tool where the executable for QRC is. How do I do that? Modifying PATH variable didn't help. Is there a command to do that?

In addition, I know for static timing analysis, coupling capacitances are not extracted seperately with setExtractRCMode -coupled false command. However, when I do timeDesign with -si option, I see some negative slack. Since the block I'm working on is a timing critical one, I need to make sure timing is accurate. You think I should take signal integrity into account for timing analysis and optimization?

Thanks!

  

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How to detect the clock glitch ?

January 1, 2014, 11:59 pm
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Hi,All 

Now , there are two clock signal in the design, the two clocks and select signal are synchronous, but the phase between them is uncertain, then use the selecting signal 'SEL' to switch the two clock dynamically. So it is possible that some glitch will occur, I want to know how to detect or check the glitch in encouter timing system intead of functional verification ?

 Thank You. 

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Algorithm used for implementation of Division

January 2, 2014, 3:27 am
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Hi

What is the default algorithm used for hardware implementation of division operation when synthesised using RC Compiler. Like the code below  

begin

quot[n:0] = divd/dvsr;

remi = divd%dvsr;

end

 Thanks in advance,

Soma 

 

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Manual CTS report

February 6, 2013, 12:20 am
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Hi everyone,

I am currently doing a project mainly focus on clock tree synthesis in Cadence Soc Encounter. As I need  to study different topology of clock trees, I am using the manual mode CTS. What I have done is:

1.use specifyClockTree command to read in the ctstch file

2.use ckSynthesis command to do the actual clock tree synthesis

3.use routeClkNetWithGuide command to do the clock net routing

After these steps, the clock tree had been synthesized, buffers had been inserted and clock nets had been routed. Beside the optimization process, I think the clock tree had been at least generated  successfully so far.

So I want to take a look about the information of the clock tree, such as skew or any other delay informations. That's why I went on use the reportClockTree command. And here comes the problem, the file generated by the command only has a title inside but nothing left.

When using the auto CTS flow,   reportClockTree works just fine.

Does anyone knows why? How can I get the report under manual cts mode? Besides, did I miss any critical step in the manual cts flow?

Thanks for any help

Regards

Yuqi 

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Manual CTS

January 6, 2014, 9:38 am
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Hi,

Please give an example to build H-tree CTS in encounter. 

Thanks,

Nitin 

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Printing common elements between 2 collections

January 7, 2014, 8:28 am
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Hi,

 Is there a quick way to print all the common elements between 2 collections. Right now I am doing to usual loop method of comparison. Please let me know if there is an easier/faster way.

 

Regards, 

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Syntax V93 VHDL

January 13, 2014, 9:22 am
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 Hi there,

 

I am building an ip, i tested it on Xilinx FPGA is seems works 

 

now i m testing it on virtuoso cadence and give me this 2 errors, someone can help please 

1) -------------------------------------

E,MLTDRV (./test.vhdl,17|0): Signal/register 'M_ADDR' has multiple drivers.
------
The specified signal/register has multiple drivers which can
be active simultaneously. This may lead to signal/register
having undefined/unexpected value and can also result in
difference in simulation and synthesis behavior.

The following parameter present in the default rules file can be used to modify the behavior of this check:
params MLTDRV {ignore_z_drivers="yes|no"}

The default value of this parameter is 'yes'. In this case, if a signal has two drivers with
one of the drivers being 'Z', the tool will allow the signal to have a 'Z' driver and a
violation will not be reported. Alternatively, when this parameter is set to 'no', the 'Z' driver
will be considered invalid and a violation will be reported.

The following example illustrates the occurrence of MLTDRV:
assign sig_a = var_a;
assign sig_a = var_b;

In the above example, 'sig_a' is multiply driven.

Line 17---  M_ADDR :   OUT std_logic_vector(31 DOWNTO 0);

Line 378---M_ADDR <= std_logic_vector(to_unsigned(1, 32))+ u2fpi; 

 

2)-------------------------------------------------------

*E,MLTDRV (./test.vhdl,19|0): Signal/register 'M_RD' has multiple drivers.
------
The specified signal/register has multiple drivers which can
be active simultaneously. This may lead to signal/register
having undefined/unexpected value and can also result in
difference in simulation and synthesis behavior.

The following parameter present in the default rules file can be used to modify the behavior of this check:
params MLTDRV {ignore_z_drivers="yes|no"}

The default value of this parameter is 'yes'. In this case, if a signal has two drivers with
one of the drivers being 'Z', the tool will allow the signal to have a 'Z' driver and a
violation will not be reported. Alternatively, when this parameter is set to 'no', the 'Z' driver
will be considered invalid and a violation will be reported.

The following example illustrates the occurrence of MLTDRV:
assign sig_a = var_a;
assign sig_a = var_b;

In the above example, 'sig_a' is multiply driven.

 

line 19 ----- M_RD  : INOUT std_logic;

line 493 --- M_ADDR <= std_logic_vector(to_unsigned(0,32))+u3fpi;

 

Thank  you so much for your help regards 

 

 

 

 

 

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Encounter Library Characterizer gate recognition fails

January 15, 2014, 6:08 am
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 Dear all,

I'm having a problem with the Encounter Library Characterizer tool in the ETS Suite.
I'm trying to characterize standard cells, however, I'm having a problem that keeps returning at a lot of forums, but never seems to get solved.

In the first step of characterization, the tool should detect the logic functions of my circuit. I'm using a simple inverter:

simulator lang = spectre
global vdd
global gnd
subckt inv A Y vdd gnd
    \+1 (Y A vdd vdd) ami06P w=6e-06 l=6e-07 as=9e-12 ad=9e-12 ps=9e-06 \
        pd=9e-06 m=1 region=sat
    \+0 (Y A gnd gnd) ami06N w=3e-06 l=6e-07 as=4.5e-12 ad=4.5e-12 ps=6e-06 \
        pd=6e-06 m=1 region=sat
ends inv

 I'm using this library (http://www.ece.umd.edu/~dilli/courses/enee408d/ami06models/ami06.lib) as a simple example to mess around with.The setup-file is this:

 // Encounter Library Characterizer setup file
Process typical{
    voltage = 5.0;
    temp = 25;
    Corner = "TT";
    Vtn = 0.67;
    Vtp = 0.92;
};

Signal std_cell {
    unit = REL;
    Vh=1.0 1.0;
    Vl=0.0 0.0;
    Vth=0.5 0.5;
    Vsh=0.8 0.8;
    Vsl=0.2 0.2;
    tsmax=2.0n;
};
   
Simulation std_cell{
    transient = 0.1n 80n 10p;
    dc = 0.1 4.5 0.1;
    bisec = 6.0n 6.0n 100p;
    resistance = 10MEG;
};

Index DEFAULT_INDEX{
    Slew = 0.100n 0.30n 0.7n 1.0n 2.0n;
    Load = 0.025p 0.05p 0.1p 0.3p 0.6p;
};

Margin m0 {
    setup     = 1.0 0.0 ;
    hold     = 1.0 0.0 ;
    release = 1.0 0.0 ;
    removal = 1.0 0.0 ;
    recovery = 1.0 0.0 ;
    width    = 1.0 0.0 ;
    delay     = 1.0 0.0 ;
    power     = 1.0 0.0 ;
    cap     = 1.0 0.0 ;
} ;

Nominal n0 {
    delay = 0.5 0.5 ;
    power = 0.5 0.5 ;
    cap   = 0.5 0.5 ;
} ;

set process(typical){
    simulation = std_cell;
    signal = std_cell;
    margin = m0;
    nominal = n0;
    index = DEFAULT_INDEX;
};

 The elccfg file in the running directory is this one:

# Setup stuff
SETUP = "setup.ss"
PROCESS = "typical"
SUBCKT = "dut.scs"
MODEL = "ami06.scs"

When I run this file in ELC:


db_open foo
set_var EC_SPICE_SIMPLIFY true
set_var EC_HALF_WIDTH_HOLD_FLAG true
set_var EC_SIM_NAME "spectre"
set_var EC_SIM_TYPE "spectre"
set_var EC_SPICE_SUPPLY1_NAMES "vdd"
set_var EC_SPICE_SUPPLY0_NAMES "gnd"
db_prepare -force
db_gate
db_close
exit

ELC does not recognize the simple inverter circuit. The resulting gate recognition is the following:

==============================
      DESIGN : INV
==============================
DESIGN ( INV );
//    =================
//     PORT DEFINITION
//    =================
    SUPPLY0 GND ( GND );
    SUPPLY1 VDD ( VDD );
    FEEDTHRU A ( A );
    FEEDTHRU Y ( Y );
//    ===========
//     INSTANCES
//    ===========
END_OF_DESIGN;

- feed-through ( A ) is found
- feed-through ( Y ) is found
 

As you can see, the A, Y ports are recognized as feedthrough, while they should be input and output ports. I've searched and read a lot about this problem, and it seems that this not so easy to solve. Especially since the variables to play with are very limited: I guess the problem can only be in the technology model, netlist, setup-file or cmd-file? I've tried (in my opinion) every reasonable alternative, and I do not seem capable to finish the flow correctly. 

Does anyone have any suggestions I can follow to overcome this problem? I know it is possible to edit/write the gate-file by hand, but since I'm planning on doing a lot of characterization, this is not really an option. Also, I would like to pass the entire flow automatically for convenience.

Any suggestions are welcome,

 Kind regards,

Hans

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