Hi,
How to verify the LVS for gds file from Cadence SE. I have used 65nm STM standard cells for generating netlist file for layout and schematic design. i am getting mismatch erros in Calibre LVS report (INCORRECT). How to avoid bulk pins (vdds, gnds) in schematic, and missing instance (nsvtlp, psvtlp) cmos065.
Thank you!!
Hello,
First run through EDI 12.00 and I'm having a few teething problems.
Successfully synthesised the RTL to verilog netlist but when I import the design I'm getting the following warnings (all standard cells are in the verilog netlist are listed, I've trucated the listing for the post).
I've checked the LEF and the cells are included.
Any ideas what I'm doing wrong?
**WARN: (ENCDB-2504): Cell OR6M2XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504): Cell OR4M1XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504): Cell NR3M1XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504): Cell AO31M2XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504): Cell DFQRM1XM is instantiated in the Verilog netlist, but is not defined.
WARN: (EMS-63): Message <ENCDB-2504> has exceeded the default message display limit of 20.
Found empty module (OR6M2XM).
Found empty module (OR4M1XM).
Found empty module (NR3M1XM).
Found empty module (AO31M2XM).
Found empty module (DFQRM1XM).
Starting recursive module instantiation check.
No recursion found.
Term dir updated for 0 vinsts of 85 cells.
Building hierarchical netlist for Cell hlt5000_toplevel ...
*** Netlist is unique.
** info: there are 91 modules.
** info: there are 0 stdCell insts.
Hi,
I have a power gated domain that I'm trying to implement that I'm having trouble with CTS.
I have 2 power domains : base_domain(always on) and gated_domain(power-gated).
Both domains have multiple clocks in the domains that I'm trying to synthesize clock tree for.
For some reason, when I perform ClockDesign, Encounter places the clock tree cells that belong in the gated_domain in the
base_domain. I tried setting -honorFence true in setCTSMode but it doesn't seem to help. The clock tree starts from the
gated_domain and crosses over to the base_domain. Is there a way to restrict the placement of clock tree
within its power domain? I cannot have the clock cells cross over from the gated_domain to the base_domain.
I did connect global power nets to all pins. Then did sroute. Then added the standard cells. And the geometry check gives me this errors, thousands of them:
Blockage of Cell U_BUF2/URAM/ram_reg[413][12]
bbox = (322.540, 1477.810) (322.600, 1478.170)
I am attaching picture pointing to the error with arrow. The blue lines you see are M1 VDD! and GND! lines, and I have checked the standard cell layout and confirmed that those power lines correctly overlap the power lines of standard cells.
I am not quite getting why the error checker is not happy and what kind of blockage of cell is it talking about? Whst exactly is blocked?
HI All,
Have a query on First Encounter tool.
I have a port(abc) which is connected to all the memory_pin(abc) in the design through aob's
I need to trace the connectivity and dump_out the complete path through that port
Second is there a way to hightlight in layout like how they are placed or view in schematic the entire path from the port to all the memories.
Can someone please help out on this like how to go on wiht or if someone could provide with a script.Need urgent support on this.
Apprecaite your help
-Thanks
Hi All,
Thanks for your time.
I have some set_max_delay settings on input and output ports.
I would like to query them in ETS. Is there a way to query them.
Ex:- I have a collection of in2reg paths and I would like to query the set_max_delay attribute( This is reported in + Path Delay of timing report)
Other End Arrival Time 1.829
- Clock Gating Setup 0.059
+ Path Delay 0.700
+ CPPR Adjustment 0.000
- Uncertainty 0.100
= Required Time 2.370
- Arrival Time 0.191
= Slack Time 2.180
I would appreciate if anybody can provide some pointers.
Regards
cosmo
Hi All,
Is there any way/tool to extract info from gds to .def file.
Regards
suraj
My SOC installation does not respond to any commands from keyboard (looks like keyboard do not exist)
So i run in severe problems because can not edit synthesis scripts etc.
All other software, including Cadence IC, is working properly.
My system is CentOS 5.4, 64 bit. I use Japanese USB keyboard.
Any suggestions?
Hi, All,
We try to fabricate our chip with MOSIS and submit our design. But
there is an error during DRC ERROR: no CHIPEDGE seen.
We ask help for MOSIS technical support and they say:
"CHIPEDGE is something you can teach Encounter to draw for you",
it is a special Encounter instruction sequence. You will have to search
your Encounter documentation to find it. Search on keywords such as "drawing a bounding box polygon" or "chamfer" or even "CHIPEDGE" might
give you a hit. With that sequence you can force Encounter to draw the
CHIPEDGE polygon directly".
We search the whole encounter document but cannot get a hit. If anyone know something like this, please help us.
We appreaciate
Thanks
We are packaging our chip with a flip-chip package (and c4 flip chip bonds).
We don't have any CLASS BUMP files all we have is CLASS PAD AREAIO for the LVDS drivers and regular drivers.
We have virtuoso layout files for a c4 pad.
We were thinking we would need a bump cell too that would be used in Encounter however.
We are wondering if we are missing a bump cell or is there some way to connect the c4 pad from Virtuoso to Encounter, and how this is done.
Thank you
Using Encounter 13.2
Defined .capTbl, .tch, .lef files, defined timing and other settings in viewdefinition. Got the design placed and routed. Once I start checking the design with verifyGeometry I see hundreds of thousands errors of different type like:
Antenna
MinArea
No-Grid
OffGrid
Spacing
Short
Using the following commands did not help:
setOptMode -fixDRC true
optDesign -preCTS
Then I used these commands:
verifyTracks
generateTracks
globalDetailRoute
Now the amount of errors after verifyGeometry check reduced to:
18 MinArea errors
171152 No-Grid errors
239 Spacing errors
So I see some improvement but I cannot get it any better yet. Those >170k MinArea errors and 239 Spacing errors tell me that something is wrong maybe with the flow or with the way how the tool interprets constraints. But I am not sure what exactly could be wrong.
The LEF files I am using are from the manufacturer and as they say were tested on many designs (the IBM 7RF Kit). So, I am assuming something is wrong on my side or in the way how I configure something.
Anyone has some ideas where else would be worth looking at?
Halo,
I am using ELC to characterise a new standard cell library. I am using a SPECTRE .scs model file, but it seems that ELC is not recognising this file format correctly, as it complains about library and section declarations which are present in the model file. I assume that my command and/or elccfg file is not set up correctly for using spectre.
This is the contents of my command file:
db_open cell_digital
db_prepare -f
db_spice -s spectre -keep_log -keep_wave
db_output -lib cell_digital.lib -process typical -state
db_close
exit
And this is the contents of my elccfg file:
# Specify the environment variable settings.
EC_SIM_USE_LSF=1;
EC_SIM_LSF_CMD=" ";
EC_SIM_LSF_PARALLEL=10;
EC_SIM_TYPE="spectre";
EC_SIM_NAME="spectre";
EC_SPICE_SIMPLIFY=1;
EC_CHAR="ECSM-TIMING ECSM-POWER";
SUBCKT="cell_digital_SPICE_netlist.scs";
MODEL="model_file.scs";
SETUP="setup.ss";
PROCESS="typical";
Can somebody guide me into the right direction?
Thank you,
I use ELC to characterize a standard cell library. I used SPECTRE simulator with TSMC model (target to Spectre). When I run ELC, there is a error message that apprears when db_spice command is run
Reading SUBCKT:NMOSCAP
[ERROR(db_prepare)] spice syntax error: NMOSCAP : redefinition of the subckt [ file = ./model/./tsmcxxxx.scs, #line = 122760 ]
=> subckt nmoscap ng nds
I had checked postes in forum and found out there is a suggestion for the case of using HSPICE simulator
http://www.cadence.com/Community/forums/p/13220/20163.aspx#20163
I followed that solution but error is remained
I also check my TSMC model file for SPECTRE simulator and it works fine however it seems that ELC can not successfully load my model.
Is there anybody having the same problem and a solution for it ?
Kind regards
/T
Hi, all
I am doing std cell characterazation using ELC. And I use a model file from TSMC, it defines multiple sections for different processes and corner. At each section, it defines many parameters which has unique values to that process and/or corner, then it include the mos model which uses these parameter to describe its characters. The ELC could direct into the right section and include the mos model well, but it seems it does not recognize the parameter definition. It reports errors when I do "db_spice". Reported errors like:
Error found by spectre during hierarchy flattening. ERROR (SFE-1999): "/home/abc/works/elc/foo.ipdb/NCH.device/simulate/model" 4: Model `nch.1': parameter `wmin': Unknown parameter name `dxw' found in expression.
This model file works well with spectre in virtuoso, but not with ELC.
Anybody could help me with this? Thanks in advance!
ps. In the elcUG dorcument, under the SPICE Input directory, it said "An optional parameter library file, which defines the device parameters for different process corners" but no more detials following. Anyone know how to write this file and how to include it in ELC project?
Hi.
I'm not sure if this is the correct forum. In case its not, please direct me to the direct one.
Problem: I'm trying to simulate the amplication circuit in ORCAD using a AC power source and LM 566.
I'm not able to get the waveform in the simulation window.
I've attached the screenshot of the circuit also.
Could anyone please help me in this.
Thanks,
Sunny
Are SITE DEFINITIONS something what designer must re-write for every cell?
Or it is something what I am supposed to receive from the foundry with the LEF file?
How does it usually work out?
thanks.
Hi,
I am using a kit which allows connecting PMOS body to ground. But once I am trying to connect them by globalNetConnect it generates short circuit error. Is there a way I can do that.
Thanks
Hi
I need a clarification for the below issue. I have a 550k+ sinks for clk_sys. To get, better skew & insertion delay values. I found out the clock gating cells & mentioned those output as "AutoCTSRootPin" lets take CLK_GATE as clock name & has some 400k+. I mentioned those in the intial portion of the ctstch file and later my main clk "clk_sys" comes up. so, it will build for "CLK_GATE" 1st then it comes to clk_sys.
As the result, am getting better skew & insertion for CLK_GATE But for "clk_sys" am getting worst values. My question is, once clock tree is built for "CLK_GATE". when it comes to clk_sys tree. Whether it will re-build "CLK_GATE" tree again?
Hope my quesion is clear. Plz let me know any more brief explanation needed.