Hello, i am beginner rtl compiler user. I have a question about synthesis with rtl compiler.
For example, i have 2 signals sig1 and sig2. In verilog code:
assign #10 sig2=sig1;
Can I to synthesis some delay between 2 signals by rtl compiler commands such 'path_delay' or others?
I am trying to generate a layout using SoC Encounter. After importing all required files and going through process, I couldn't see the VDD and VSS are connected. They are left unconnected in the layout. I tried to figureout if somewhere I gone wrong but steps are followed stringenlty. I have simplified to understand the issue and generated D FF using SoC. Kidnly check the attachment and help me out in understanding the issue.
Thank You.
Where can I find a template for gate array style layout using Encounter? Any pointer/hint/help is appreciated. Pardon me if this is not a proper forum. Thanks.
Well this is my very first post here so first of all good afternoon!
Here is my problem :
I'm using Encounter to place and route an IP in which i want to space somes instances of the same standard cell by a fixed value.
What i've found in the lefdef reference manual (version 5.8) is to use the SPACING attribute of an IMPLANT layer as explained in pages from 154 to 156.
I've defined a rectangle which is not covering the whole standard cell in the horizontal direction (to avoid the abutment case) in the OBS section by using the implant1 layer i've created in the technology lef. My spacing rule is set but it looks like Encounter is not taking this into account as the cells are still very close one to another.
What i want is to have what is described in the lefdefref manual in Figure 1-75 on page 156.
I've read about the honorImplantSpacing option but this is quite different as it requires to have at least two implant layers.
Thanks a lot if anybody here can help!
Best Regards.
i had design a divider and a up/down counter for a section of my project.Input frequency of clock is 50mhz and it is divided by 50(1mhzclock) to clock up/down counter.but after synthesis their exist a timing problem to registers define for up/down counter
timing problem is
THE FOLLOWING SEQUENTIAL CLOCK PIN HAVE NO CLOCK WAVEFORM DRIVING THEM.NO TIMING CONSTRAINE WILL BE DERIVED FOR PATH LEADING TO AND FROM THESE PINS(which is registers define in up/down counter)
so how can i define clock(1mhz) to up/down counter(which is divided from input clock of 50mhz)?
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Hi all,
I've ran into a particularly a troublesome error while running SOC Encounter.
I'm currently implementing a design starting from behavioral verilog, synthesizing using Design Compiler
and then running place and route using SOC Encounter.
The problem is that the verilog netlist produced by SOC Encounter does not seem to match functionally with the
behavioral verilog and synthesized verilog. The synthesized verilog works fine, but the place and routed design
produced by encounter is functionally incorrect when simulted under the same conditions.
Has anybody experienced anything like this, and does anybody know how to ensure that Encounter produce a functionally
correct design? My guess is that encounter does something wrong while re-synthesizing during timing optimization. This is an important issue.
Hello All,
I am trying update the script for DEI13.2, and have some issue while doing postRoute optimization. The old script line is as following:
optDesign -postRoute
The following error shows up in the report:
**ERROR: (ENCOPT-7016): use setDelayCalMode -engine [feDC | signalStorm] -SIAware false before running optDesign -postRoute -si [-hold].
I changed the command to:
setDelayCalMode -engine feDC -SIAware false
optDesign -postRoute -si
I got two errors shown as following: (similar results while using signalStorm option.)
**ERROR: (ENCOPT-7071): The distributed optimization engine is obsolete and has been replaced by the GigaOpt optimization engine which is default in this release. Please update your scripts to remove any explicit settings of 'setDelayCalMode -engine feDc' or 'setDelayCalMode -engine signalStorm' so you get the default Advanced Analysis Engine (AAE) delay calculator to enable the GigaOpt engine.
**ERROR: (ENCSYT-6692): Invalid return code while executing 'encounter.tcl' was returned and script processing was stopped. Review the following error in 'encounter.tcl' then restart.
Taking that AAE is enable by default, I tried directly
optDesign -postRoute -si
This time I got two errors
**ERROR: (ENCOPT-7016): use setDelayCalMode -engine [feDC | signalStorm] -SIAware false before running optDesign -postRoute -si [-hold].
**ERROR: (ENCOPT-6080): AAE-SI Optimization can only be turned on when the timing analysis mode is set to OCV.
To run optimization while taking into account on chip variation, set an MMMC environment with the right operating condition.
Looks like I cannot do -si analysis without turning on the OCV. I checked in the user guide, and turned on the OCV mode as following (I have set a BC lib and a WC lib in the operating conditions):
setAnalysisMode -analysisType onChipVariation -cppr both
optDesign -postRoute -si
I got the following errors:
**ERROR: (ENCOPT-7016): use setDelayCalMode -engine [feDC | signalStorm] -SIAware false before running optDesign -postRoute -si [-hold].
**ERROR: (ENCSP-2002): Density too high (100.0%), stopping detail placement.
**ERROR: (ENCSP-9022): Command 'refinePlace' completed with some error(s).
The first error shows up again! The last two errors are new, and I guess they are related to the OCV mode, which I might not used properly.
To summarize, I have two questions:
1) Does the **ERROR: (ENCOPT-7016) for the old script mean NO postRoute optimization is done?
2) As suggested, AAE delay calculator is by default, why does the **ERROR: (ENCOPT-7016): show up for the old script?
3) How important is it to run optDesign -postRoute -si? Is it a common practice to run it in EDI13 or newer level?
4) Can I do optDesign -postRoute -si option without turning on OCV mode?
5) If I have to turn on the OCV mode to run optDesign -postRoute -si, what is the correct way to do it? (I tried the example script in user guide, but I got some new errors as shown above.)
Sorry for so many questions, I am not very familiar to this flow. Any comments are highly appreciated.
Hello All,
I need your suggestions the warnings I got in the report after P&R with Encounter. The warning information is as following:
Parse map file...
**WARN: (ENCOGDS-399): Only 2 layer(s) (M2 M3) of a VIAFILL object is(are) specified in map file 'tsmc090.map'. A VIAFILL object needs 3 layers (M2 VIA2 M3) being specified at the same time in the map file. Add VIAFILL contruct(s) to the map file for the following layer(s): VIA2 or remove VIAFILL construct(s) from the map file for the following layer(s): M2 M3.
**WARN: (ENCOGDS-399): Only 2 layer(s) (M2 M3) of a VIAFILLOPC object is(are) specified in map file 'tsmc090.map'. A VIAFILLOPC object needs 3 layers (M2 VIA2 M3) being specified at the same time in the map file. Add VIAFILLOPC contruct(s) to the map file for the following layer(s): VIA2 or remove VIAFILLOPC construct(s) from the map file for the following layer(s): M2 M3.
As the warning suggested, I should add Add VIAFILL contruct(s) to the map file for the following layer(s): VIA2. I don't know how to add VIAFILL only to VIA2. I tried to change VIA1 with ALL layers, shown with underline. The warning information for M1 and M2 went away.
#-------------------------------------------------------------------------------
#SOC Layer Name SOC Layer Type GDS Layer Number GDS Layer Type
#============== ============== ================ ==============
#VIA1 VIA 51 0
VIA1 ALL 51 0
Question: I am nor sure whether the way I updated the .map file is correct or not although the warning information does disappear. Could you please tell me how to do this correctly, or any reference to generate correct .map file?
Thank you, and the .map file I am using is as following:
The information in the .map file: (tsmc90)
#-------------------------------------------------------------------------------
#SOC Layer Name SOC Layer Type GDS Layer Number GDS Layer Type
#============== ============== ================ ==============
M1 NET 31 0
M1 SPNET 31 0
M1 PIN 31 0
M1 LEFPIN 31 0
M1 FILL 31 0
M1 FILLOPC 31 0
M1 VIA 31 0
M1 VIAFILL 31 0
M1 VIAFILLOPC 31 0
M1 LEFOBS 31 0
NAME M1/NET 31 0
NAME M1/SPNET 31 0
NAME M1/PIN 31 0
NAME M1/LEFPIN 31 0
#M1 ALL 31 0
#NAME M1/NET 31 0
#NAME M1/SPNET 31 0
#NAME M1/PIN 131 0
#VIA1 VIA 51 0
VIA1 ALL 51 0
M2 ALL 32 0
NAME M2/NET 32 0
NAME M2/SPNET 32 0
NAME M2/PIN 132 0
VIA2 VIA 52 0
M3 ALL 33 0
NAME M3/NET 33 0
NAME M3/SPNET 33 0
NAME M3/PIN 133 0
VIA3 VIA 53 0
M4 ALL 34 0
......
Hi,
I encountered below error, how should this be solved?
#1 WARNING(SPMHNI-184): Device library warning detected.
WARNING(SPMHNI-198): Problems with device 'PIC16F1829-SOIC20,MICROCHIP TEA'. Pinname'CCP2/P2A/T1CKI/SD02/T1OSI/OSC1/CLKIN/RA5' is replaced by '$0': 'Pin name is not legal.'. [help]
Thanks,
Mabel
Hi all,
New to this area, I have two questions that need your help.
1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get comfused, under which input pattern does the Compiler infer all the power values, especially switching power, since it's directly related to the frequency of input?
2nd, what's the difference between Leakage Power and Internal Power? And does Net Power means power consumed from the interconnect? I get confusion about these terms
Thank you very much for your notice and help!
Best
Hi,
I am doing some digital design now. After finishing PnR with Encounter, I exported a DEF file. But when I import this DEF file into Virtuoso, the via array is mssing. Only the VIA ARRAY which is on power ring is missing, other single via is fine. How to fix it?
could anyone help me? Thanks in advance!
Hi,
I have a requirement add dummy power net which has to conected to macro pins.
with "addNet -physical only " I could able to create the net. But it is not created as global net.
When I do a globalnetconnection to the macro pins I am getting an error that the net created is not a global net.
can any one suggest me to add a global net and conect it to a pin in encounter.
Thanks and Regards, Anil
Hi,
When we are trying to do parasitic extraction with the QRC 13.10.302 version, tool is getting hanged at capacitance extraction stage & not going to the output generation stage.
We have even tried by using distributed processing also. Still it is of no use.
Your quick response is appreciable.
Thanks & Regards,
Sanath
Can someone tell me what exactly it meant by "NF GOLDEN"
I got this as comment when i tried to generate the difference in XCAP between to spefs (the difference here shows as 999 and 99.99%)
Please help me in this issue
Thanks in advance
Hi All ,
Can any one give solution for the following issue ,
There are three power domains in my block , while doing optimisation the domain crossing nets (clock and signal) are not optimising.
I am using EDI11.0 version , what are the sollutions to optimise domain crossign nets.
I would like to adapt DEF flow with RTL compiler PLE.
Is there any user guide or manual I can reference with?
And should I get a detailed DEF from backend or I can just take a rough DEF (only information about memory, hard macro, and some high level hierarchical design)?
thanks!