I am running dynamic power analysis on my design . When the set_power_analysis_mode -method dynamic_vectorbased is set and VCD file is given , report_power command should generate the dynamic current data files (ptiavg files) for all the PG nets. However , when I run the report_power command it is not generating the ptiavg files for the power nets of the macros.In static power analysis the ptiavg files for all the nets are being generated. Also the rest of the dynamic power analysis script remaining the same, if I change the set_power_analysis_mode -method to static, the static current data files are being generated for all the nets. What could be the possible reason for the dynamic current files of macros not being generated?![]()
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Dynamic Power Analysis
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Netlist help for switch block
Hello everyone,
I am new to the pspice netlist, Could any body give some help on implementing Switch block of the FPGA.
Thank YOu
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Macro Power Routing
Suppose we have a macro having pins(vertical) on layer M4. We have to drop VIAs from M8(Horizontal)stripe. I used the following command
" editPowerVia -add_vias 1 -selected_blocks 1 -top_layer M8 -bottom_layer M4 -orthogonal_only 1 -same_sized_stack_vias 1"
But the tool can not drop via appropriately
Would please someone help
Thanks
Tanvir Hasnain Shovon
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Active analysis view
Hello!
I am new to Cadence EDI. I am currently using Encounter 13.2
How can I find the current "active analysis view"? There is a command "all_analysis_view", but it gives all the views defined in viewDefinitions file not the active ones.
Thank you in advance.
Regards,
Imdad
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Setting Timing Derate
Hi I am shovon
New to encounter. So facing syntax related problem .
How can i apply diffrent derating factors for setup and hold in OCV.
It will be helpful if anyone elaborate about setting different derating factors according to mode and check type for a particular delay corner. That is I want to set different derating factor for different analysis view.
Thanks
Tanvir Hasnain Shovon
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Connecting Global power to Pins of instances
Sometimes I noticed when you do operation of connecting global power to pins of instances and then do Check operation it says that power is not connected to some instances.
I am curious is it something normal? Does it mean that specific instances are kind of optimized? Or should I be worried about it?
All my instances have VDD! and GND! power pins, and I defined global VDD! and GND! power. In some designs for example, when I choose that operation and then do the Check, it says nothing. i.e. everything is connected, but on another designs (it actually depends on a code) it gives warning that some pins were not connected.
How does that thing usually work out?![]()
I am curious is it something normal? Does it mean that specific instances are kind of optimized? Or should I be worried about it?
All my instances have VDD! and GND! power pins, and I defined global VDD! and GND! power. In some designs for example, when I choose that operation and then do the Check, it says nothing. i.e. everything is connected, but on another designs (it actually depends on a code) it gives warning that some pins were not connected.
How does that thing usually work out?
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via size
when I try to add via with this command:
editPowerVia -add_vias 1 -via_rows 3 -via_columns 1 -top_layer M8 -bottom_layer M5 -orthogonal_only 1, it shows following warning and vias are not added.
**WARN: AddVia Warning: can't specify cut numbers for stack vias
**WARN: AddVia: please specify via size instead
how can I specify via size?
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clock uncertainty
Hello All!
How can I define different uncertainty value for different delay corners (i. e WCL_rcworst_-40) in encounter?![]()
How can I define different uncertainty value for different delay corners (i. e WCL_rcworst_-40) in encounter?
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SoC Encounter - Hierarchical design help
I am running into an issue while trying to implement a hierarchical design in Encounter. My design has 4 different types of modules instantiated in the top level. After importing the gate level netlist into Encounter, I switch to floorplan mode and see a box for the core and a solid pink box for one of the modules instantiated in my design. The other 3 modules do not show up at all. However, when I open the design browser I see that it lists all 4 modules. I can't figure out why these modules don't show up while in floorplan mode. Can anyone give me some suggestions or guidance? Thanks.![]()
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REG CADENCE Encounter 90nm/65nm library Files
Hello,
I would like to know some info. regarding Library files thaat are req for my CADENCE Project at nodes 90nm and 65nm.
what are the necessary files that i need to have when i mean 90nm library files for Encounter. My prof like to get them. SO i am eager to knwo what should be the files so that i will not get any errors when i import my design.
Please help me.
Let me know if you need more info.
Thanks,
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leafpingroups leafcellgroups?
Looking for documentation cnnot find anything about this in FETXTCMDREF.....where should I look to find everything about clock tree synthesis including the Azuro features
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Problem with ELC tool
I use ELC to characterize a standard cell library. I used SPECTRE simulator with TSMC model (target to Spectre). When I run ELC, there is a error message that apprears when db_spice command is run
Reading SUBCKT:NMOSCAP
[ERROR(db_prepare)] spice syntax error: NMOSCAP : redefinition of the subckt [ file = ./model/./tsmcxxxx.scs, #line = 122760 ]
=> subckt nmoscap ng nds
I had checked postes in forum and found out there is a suggestion for the case of using HSPICE simulator
http://www.cadence.com/Community/forums/p/13220/20163.aspx#20163
I followed that solution but error is remained
I also check my TSMC model file for SPECTRE simulator and it works fine however it seems that ELC can not successfully load my model.
Is there anybody having the same problem and a solution for it ?
Kind regards
/T
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SoC Encounter - Timing Report Confusion
I'm sorry if this is a basic question, I am new to using encounter.
During synthesis, i set constraints on the clock like clock_latency and uncertainty to synthesize assuming a pessimistic clock distribution. Based on my understanding these parameters make sure to create a pessimistic setting in synthesis to make sure the design meets timing. I understand these so far and mostly how they affect the synthesis and the design.
My main question is, once I move on to place and route in encounter. I feed the
synthesized netlist and a *.sdc file which includes all these constraints to
encounter for place and route. I am able to place and route everything and see
my timing reports. BUT it seems that the timing reports, STILL use these
constraints from synthesis. I feel like they shouldn't anymore, since the clock
tree has already been synthesized in encounter, the tool should just use that
for timing, and not rely on settings I had in synthesis. I was wondering if I need
to set anything special in encounter to make sure that the timing reports
reflect the synthesized clock tree and not the constraints I set in synthesis of
the RTL.
Any feedback anyone can give me would be appreciated.
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Programmable Logic Wizard Problem
Hi everyone,
I'm having a trouble creating a new project using the programmable logic wizard in OrCAD Capture. The vendor and family list is empty so I can't create a new project. How to fix this issue? Please help me as I'm fairly new to this software.
Thanks.
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No driven nets
Dear all,
I am facing an issue with Encounter which i do not understand.
In my digital block I forward my clock input to another clock output pin on my digital block.
VHDL : CLK_OUT <= CLK_IN;
The reason why I am doing this is that my digital block creates some outputs (I will name them DIG_OUT here..) which are clocked with the CLK_IN clock port,
These outputs with the forwarded CLK_OUT clock are fed to another separate block somewhere else on chip in the same mixed signal die.
In order to constrain my DIG_OUT ports with respect to the CLK_OUT port i used the following contraints:
First I constrained my CLK_OUT :
create_generated_clock -name clk_output_clock -source [get_ports CLK_IN] -multiply_by 1 [get_ports CLK_OUT]
Then I constrained my output port DIG_OUT:
set output_delay -clock [get_clocks {clk_output_clock}] -max [expr $tSU] [get_ports {DIG_OUT
set output_delay -clock
, where $tSU and $tH represents the worst case setup and hold time of the receiving flipflops in the other digital design further away on the die. Trace length between data and clock lines from DIG_OUT and CLK_OUT to the destination digital block on the die are equal.
After clock tree synthesis, and mapping to the final layout of my final design I can see that encounter has included one clock buffer between the CLK_OUT and CLK_IN port together with some connecting traces. I can see these element in my layout so that is good.
However, Encounter reports show one report which I really do not understand, a no-drivenNets report:
No-driven Nets Information Page
* TODO:
assign_net_CLK_OUT_0
assign_net_CLK_OUT_1
CLK_IN__Exclude_0_NET
The corresponding mapped layout verilog shows a connection from CLK_IN to an clk buffer and the output of the clk buffer to the CLK_OUT pin.
Generated verilog gives this:
cnbfx2 CLK_IN__Exclude_0 (.Z(CLK_OUT),
.A(CLK_IN));
However, it seems as if the connecting traces in the layout are not connected in the corresponding verilog (although they are clearly visible and connected in the layout..).
Can anybody explain me what is happening here and why this only occurs with this buffererd output clock signal?
With kind regards,
Henk
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I need help in replacing transistors
Hi all,
I'm using virtuoso 6.1.4
I have a library that contains alot of schematics with alot of transistors.
My problem is :I want a fast way or methode to REPLACE all of these transistors from (let's say 130nm technology) to ( 65nm technology tsmc or something like that) keeping the W/L ratio,i can do that manually (one by one) but that will take very very long time,i believe that there must be an easier way to do that ,i mean if there is a command can be written in Comman Line Interface CLI that will be great !
Thanks in advance
Ammar Abdou
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encounter -error while loading design
**ERROR: (SOCLF-82): Macro "DFSECP1" obs coordinate y value 9.0740 isn't on
manufacturing grid. It's likely result in placement/routing that can't be manufactured How could i solve this error?![]()
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offRGrid option using verifyGeometry
Hi,
When I use verifyGeometry command without any option, I get just 4 violations, but when I specify the -offRGrid option, I get a lot of no grid violations.This is because of some filler cells which have pins which do not intercept the routing grid.
Is this possible ? Why would we put some pins on filler cells which are not on the routing grid ?
Aditya
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CelticSignalStorm vs. AAE, holdviolations
Hi there,
we are using Encounter 13.1 and changed the from SignalStorm flow to AAE flow.
While porting our scripts we found out, that even if AAE optimizes the design and fixes all hold violations,
SignalStorm still finds hold violations. So is SignalStorm more pessimistic?
We now use the following script for postRoute optimization:
...
setAnalysisMode -analysisType onChipVariation -cppr both
setDelayCalMode -SIAware true -engine default
# In-Place-Optimization
setOptMode -usefulSkew true
#step -> optimizatzion effort
for {set step 0} {$step <= $Effort} {incr step} {
if {$step==0} {
optDesign -postRoute
if { $::SOC_FIX_HOLD == 1 } {
optDesign -postRoute -hold
}
} else {
optDesign -postRoute -incr
if { $::SOC_FIX_HOLD == 1 } {
optDesign -postRoute -hold -incr
}
}
}
#switch engine to use slow but more accurate Signal Storm optimization
#for setup and hold optimization with signal integrity optimization enabled
setDelayCalMode -engine signalStorm -SIAware false
optDesign -postRoute
if { $::SOC_FIX_HOLD == 1 } {
optDesign -postRoute -hold
}
if { $::SOC_FIX_HOLD == 1 } {
optDesign -postRoute -hold -si
}
optDesign -postRoute -si
}
So our question is, why are there still hold violations using AAE for optimization and SGS for timing analysis?
Is our flow the right way or do you have any suggestions for handling this issue ?
Kind regards,
Marten![]()
we are using Encounter 13.1 and changed the from SignalStorm flow to AAE flow.
While porting our scripts we found out, that even if AAE optimizes the design and fixes all hold violations,
SignalStorm still finds hold violations. So is SignalStorm more pessimistic?
We now use the following script for postRoute optimization:
...
setAnalysisMode -analysisType onChipVariation -cppr both
setDelayCalMode -SIAware true -engine default
# In-Place-Optimization
setOptMode -usefulSkew true
#step -> optimizatzion effort
for {set step 0} {$step <= $Effort} {incr step} {
if {$step==0} {
optDesign -postRoute
if { $::SOC_FIX_HOLD == 1 } {
optDesign -postRoute -hold
}
} else {
optDesign -postRoute -incr
if { $::SOC_FIX_HOLD == 1 } {
optDesign -postRoute -hold -incr
}
}
}
#switch engine to use slow but more accurate Signal Storm optimization
#for setup and hold optimization with signal integrity optimization enabled
setDelayCalMode -engine signalStorm -SIAware false
optDesign -postRoute
if { $::SOC_FIX_HOLD == 1 } {
optDesign -postRoute -hold
}
if { $::SOC_FIX_HOLD == 1 } {
optDesign -postRoute -hold -si
}
optDesign -postRoute -si
}
So our question is, why are there still hold violations using AAE for optimization and SGS for timing analysis?
Is our flow the right way or do you have any suggestions for handling this issue ?
Kind regards,
Marten
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tf 2 tech LEF
Hello,
Is there any tool or script to translate from TF (Virtuoso) to tech LEF format? It looks that both of them have the similar data, but we need the LEF for encounter P&R.
Thanks,
Boris
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