hello everybody,
can any body please explain why leakage power is more in lvt cells.what is relation between Vt and leakage.inversion can be acheived early if my Vt is less.how it vl effect leakage. i am searching for this answer for long time .can any body please answer this
How to do boundary optimization in soc encounter.
By following we can fix boundary timings
setClockDomains -fromType input -toType register & setClockDomains -fromType register -toType output
But, here I want to optimize for one or multiple port timing for high fanout ports like reset, etc..
Thanks
Gopi Premala
Hi,
I’m working with the technology which doesn’t have ROM. So I need to implement it by tie cells or any other way.
Does Encounter have a solution for such a case, or may be somebody has an experience with custom (from lib cells) ROM design?
Thanks...Boris
I am trying to create a standard cell library with transistor level model written in verilog A.
I am getting the following output
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
Simulation Summary
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
-------------+-------------+----------+--------------+-----------
-------------+-------------+----------+------------+-----------+------------
DESIGN | PROCESS | #ID | STAGE | STATUS | IPDB
-------------+-------------+----------+------------+-----------+------------
INVX1 typical D0000 SIMULATE FAIL all_cells_tfet
INVX1 typical D0001 SIMULATE FAIL all_cells_tfet
-------------+-------------+----------+------------+----------
When I checked the log file for error. I see " Simulation failed with status 512".
What does this error mean? Can anyone help me fix this issue?
Thanks
Rangha
Hi all,,,
Nr. of Subtrees : 118
Nr. of Sinks : 18810
Nr. of Buffer : 3231
Nr. of Level (including gates) : 23
Root Rise Input Tran : 100(ps)
Root Fall Input Tran : 100(ps)
Max trig. edge delay at sink(R): tri_des_B/des3/u2/L10_reg_14_/CK 2192.4(ps)
Min trig. edge delay at sink(R): ahbSlaveIF/readData_sel_reg/CK 2025.9(ps)
(Actual) (Required)
Rise Phase Delay : 2025.9~2192.4(ps) 0~1000(ps)
Fall Phase Delay : 2076.3~2257.4(ps) 0~1000(ps)
Trig. Edge Skew : 166.5(ps) 100(ps)
Rise Skew : 166.5(ps)
Fall Skew : 181.1(ps)
Max. Rise Buffer Tran : 304.4(ps) 300(ps)
Max. Fall Buffer Tran : 317.4(ps) 300(ps)
Max. Rise Sink Tran : 388.4(ps) 100(ps)
Max. Fall Sink Tran : 405.2(ps) 100(ps)
Min. Rise Buffer Tran : 25.9(ps) 0(ps)
Min. Fall Buffer Tran : 25.1(ps) 0(ps)
Min. Rise Sink Tran : 15.3(ps) 0(ps)
Min. Fall Sink Tran : 14.4(ps) 0(ps)
view cipher_func_mode_rcworst_corner_view : skew = 166.5ps (required = 100ps)
view cipher_func_mode_rcbest_corner_view : skew = 76.4ps (required = 100ps)
Can any explain the skew of my design from report?
What are the implications of placement density?
How to determine the optimum placement density for a design?
During ECO process, i have to add a few flops. However i don't know which level of the clock tree these flops have to be connected?
Is there a way by which the tool automatically detects/connects these flops to the corresponding clock tree and not affect the skew and still meet the timing?
Are there any guidelines as to how to perform clock ECOs for the newly added flops?
Hi,
I want to add tap cells manually around a placement blockage.
So can any 1 help me out how to do this
Like how to call in the tap cells within the design and place them like a macro around the blockage and freeze their location
Or is there any other better way to do this.
Would appreciate if any1 could help on this soon
thanks
Hi All,
Here is a stack trace situation in encounter. Even in 9.1 . Any design can be used to replicate this crash.
createPinGroup nLeft -pin {ILEAD_OFF[0] ILEAD_OFF[1]}
createPinGuide -edge 1 -netGroup nLeft
Encounter terminated by internal (SEGV) error/signal...
*** Stack trace in log file.
################################################
Explanation:
Im my group some folks inadvertenly used -netGroup instead of using correct option -pinGroup.
In -7.1-USR3-s219_1 we get this message without crash.
**ERROR: (SOCPTN-904): Cannot create pin guide because no net group is found with the name [nLeft]. Check the net group name specified and try again.
The newer version should also give similar ERROR rather then crashing.
Thanks,
Irfan
Hi,
For writting a script, I need to find all the paths that a connected to an endpoint of a particular flop with slack values.
I have three flops( ff3 , ff31 , ff32) communicating with ff4. I need to find the names of these 3 flops using script.
I tried:
puts [get_object_name [get_property [ report_timing -to ff4/D -nworst 3 -collection] launching_points]]
This is only giving me only 1 launch point ff31/CK.
How to get the list of all the flops???
Hi,
Can anyone tell me what is the diff between checkDrc and verify geometry.
Why we are getting too many violations while using checkDrc command.
why should we use verify geometry instud of checkDrc to check the drc issues in the design
what is differnce in following modes:
1.scan shift mode
2.scan capture mode
3.rambist mode
4.funtional mode
5.test mode
ple any one explain me
Hi,
When I try to place standard cells into the floorplan, I notice that the cells are not averagely distributed, no matter how I set the utilization percentage. Please check out the attacked picture. I even tried the utilization of 200%, and there still be some space forced to be empty. Conversely, the placed cells are heavily overlapping with each other in the rest area. I understand that a common setting of 70% utilization has no overlapping issue. But I am confusing with the exist of the empty wasted space. Is there anything I missed? Thanks.
Best regards,
Hi All,
as i now we can find the don't use cells in the design using get_attribute command. But i want to find don't use cells in the design using dbGet commands.
Thank you
Phanendra
I have meet lots of "end of line problems".
They are all about the distance of the lines for the standard cells.
I also attached one example.
How do I solve this kind of problems?
Thanks.
Are any of the EDI algorithms / stages optimized for the new Intel Xeon cpu's ?
For placeDesign + optDesign -preCTS I am only seeing a 7% runtime improvement.
E5-2690 14hours vs X5680 15hours probably due to the 1600 vs 1333 mem speed.
According to Intel most of the improvements are in the FPU.
Other FP intensive applications such a Matlab are showing 50-60% runtime improvement : )
Shawn
I'm using layer 3 and layer 4 for the power routing, so there are many vias through layer 3, layer 2 to layer 1.
Then there are some short circuit problems when some signals pass through the vias. Is there any option to avoid this kind of problems? Can't the tool detect these short problems and avoid these?
Thanks.
Hi all,
Can some one explain What is OCV ? I am confused that,
--> applying derates is what OCV is ? or
--> using two different libs for same (setup/hold) analysis for launch and capture is OCV ?
and What is the MMMC ?
Thanks,
smachha.
I am looking for commands in Encounter that will group cells together in close proximity, but I can't seem to find them. The commands would be similar to magnet_placement, create_rp_group, and add_to_rp_group in IC Compiler.
Can someone give me the names of the commands or a script that would have a similar effect?
Thank you!