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Nanoroute Problems (Can we do "routeDesign -globalDetail" Twice?)

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Hi all,

I was doing PnR these two days and found a very strange problem. The command I used is listed as follows:

setNanoRouteMode -quiet -drouteUseMultiCutViaEffort medium
setNanoRouteMode -quiet -routeInsertAntennaDiode true
setNanoRouteMode -quiet -routeWithSiDriven true
setNanoRouteMode -quiet -routeWithTimingDriven true
setNanoRouteMode -quiet -routeTdrEffort 7
setNanoRouteMode -quiet -drouteMinLengthForWireSpreading 1
setNanoRouteMode -quiet -drouteEndIteration default
setNanoRouteMode -quiet -routeWithSiPostRouteFix true
routeDesign -globalDetail

After this command, I check the setup time and got the following answer:

************************************************************************************ 

+--------------------+---------+---------+---------+---------+---------+---------+
|     Setup mode     |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|           WNS (ns):| -0.229  | -0.229  |  0.000  | -0.083  | -0.032  | -0.013  |
|           TNS (ns):|-728.641 |-723.595 |  0.000  | -4.608  | -0.469  | -0.076  |
|    Violating Paths:|  8883   |  8618   |    0    |   218   |   48    |   10    |
|          All Paths:|  47815  |  44315  |  29212  |  1557   |  1040   |  1935   |
+--------------------+---------+---------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|                |              Real             |       Total      |
|    DRVs        +------------------+------------+------------------|
|                |  Nr nets(terms)  | Worst Vio  |  Nr nets(terms)  |
+----------------+------------------+------------+------------------+
|   max_cap      |      0 (0)       |   0.000    |      0 (0)       |
|   max_tran     |    670 (6162)    |   -0.124   |    670 (6162)    |
|   max_fanout   |    314 (314)     |    -36     |    344 (344)     |
+----------------+------------------+------------+------------------+

Density: 91.472%

************************************************************************************

Right after the setup-time check, I do the routeDesign again:

routeDesign -globalDetail

Because the cells are already routed, the tool doesn't reroute the design as I expect.

The problem comes now. When I perform the routeDesign for the 2nd time, since the tool doesn't do any changes for me, I expect the timing should be the same, but what's weird is, I perform another timing check and got the following report:

************************************************************************************  

+--------------------+---------+---------+---------+---------+---------+---------+
|     Setup mode     |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|           WNS (ns):| -0.095  | -0.095  |  0.000  | -0.016  |  0.013  |  0.034  |
|           TNS (ns):|-147.190 |-147.163 |  0.000  | -0.027  |  0.000  |  0.000  |
|    Violating Paths:|  5537   |  5533   |    0    |    4    |    0    |    0    |
|          All Paths:|  47815  |  44315  |  29212  |  1557   |  1040   |  1935   |
+--------------------+---------+---------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|                |              Real             |       Total      |
|    DRVs        +------------------+------------+------------------|
|                |  Nr nets(terms)  | Worst Vio  |  Nr nets(terms)  |
+----------------+------------------+------------+------------------+
|   max_cap      |      0 (0)       |   0.000    |      0 (0)       |
|   max_tran     |     51 (415)     |   -0.053   |     51 (415)     |
|   max_fanout   |    314 (314)     |    -36     |    344 (344)     |
+----------------+------------------+------------+------------------+

Density: 91.472%

************************************************************************************

I'm pretty sure the tool doesn't do any changes. I checked the log file and found the designs with one "routeDesign" and two "routeDesign" commands have identical numbers of wires/via/wire-length on each metal layer. But what's strange is, they have different setup time performance, with the second one a lot better than the former one.

What happens here? Which one is the real one? I'm pretty confused so wanna ask if there's anyone willing to answer this, and/or check this problem with your own design? This problem can be easily verify, you just need to do routeDesign, check the timing, immediately do routeDesign again, and check the timig again. Compare the reports and see if you found anything different. Thanks a lot!


Clock Gating

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I am writting a script where I need to find out all the flops connected to a particular integrated clock gating cell??

when i am using

report_timing -from "ICG_name" 

This is giving me unconstrained path. 

 

 

gray code

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Hi,

I would like to know if the type of code for the state machines is configurable in encounter, in particular gray code. Thanks. 

How to add tap cells

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Hi,

I want to add tap cells manually around a placement blockage.

So can any 1 help me out how to do this

Like how to call in the tap cells within the design and place them like a macro around the blockage and freeze their location 

Or is there any other better way to do this.

Would appreciate if any1 could help on this soon

 

thanks 

How to bring up a tk form in EDI?

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Hi all,

I wish to add a GUI to my hand-crafted tcl procedures, but I cannot figure out how to bring up the tk form in SOC encounter. Yes, I can see "pack" command under EDI shell, but it turns out to be in-effective.

For a very simple example:


   button .btn1 "Button"
   pack .btn1

can create a form with one button under wish shell, but nothing happens under EDI shell. Can you help me how to deal with it? Or can i use something else to build up my own GUI?

 

Thank You,
Robin  :)

 

Useful Skew

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I have a design with 4 flops and slack values corresponding to paths are  0.2, -0.1 and 0.2.

In case of useful skew which approach is better.?

1.Making the second flop early.

2.Making the third flop late. 

EDI101 'accu.vh' not found.

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 Hi,

 I am only administrator, not a designer. I finished installing EDI101 in order for community to use encounter. They have a .tcl file that they used with previous version of encounter on Sparc. Mst probably sparc platform has nothing to do with error. Here is the message I receive.

 

 encounter -init encounter.tcl
Checking out Encounter license ...
Encounter_Digital_Impl_Sys_XL 10.1 license checkout succeeded.
You can run 2 CPU jobs with the base license that is currently checked out.
If required, use the setMultiCpuUsage command to enable multi-CPU processing.
This Encounter release has been compiled with OA version 22.04-p013.

*******************************************************************
*   Copyright (c)  Cadence Design Systems, Inc.  1996 - 2011.     *
*                     All rights reserved.                        *
*                                                                 *
*                                                                 *
*                                                                 *
* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright   *
* law and international treaties.  Any reproduction, use,         *
* distribution or disclosure of this program or any portion of it,*
* or any attempt to obtain a human-readable version of this       *
* program, without the express, prior written consent of          *
* Cadence Design Systems, Inc., is strictly prohibited.           *
*                                                                 *
*                 Cadence Design Systems, Inc.                    *
*                    2655 Seely Avenue                            *
*                   San Jose, CA 95134,  USA                      *
*                                                                 *
*                                                                 *
*******************************************************************

@(#)CDS: Encounter v10.13-s292_1 (32bit) 08/15/2012 15:12 (Linux 2.6)
@(#)CDS: NanoRoute v10.13-s033 NR120726-2234/10_10_USR3-UB (database version 2.30, 132.4.1) {superthreading v1.16}
@(#)CDS: CeltIC v10.13-s064_1 (32bit) 06/28/2012 06:48:30 (Linux 2.6.9-89.0.19.ELsmp)
@(#)CDS: AAE 10.13-s008 (32bit) 08/15/2012 (Linux 2.6.9-89.0.19.ELsmp)
@(#)CDS: CTE 10.13-s020_1 (32bit) Aug 15 2012 06:35:34 (Linux 2.6.9-89.0.19.ELsmp)
@(#)CDS: CPE v10.13-s240
--- Starting "Encounter v10.13-s292_1" on Tue Oct 30 16:50:50 2012 (mem=46.1M) ---
--- Running on hostname.domainname.com (x86_64 w/Linux 2.6.18-308.el5) ---
This version was compiled on Wed Aug 15 15:12:02 PDT 2012.
Set DBUPerIGU to 1000.
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
Sourcing tcl/tk file "encounter.tcl" ...
Reading config file - ./encounter.conf
**WARN: (ENCEXT-1085):    Option 'rda_Input(ui_res_scale)' used in configuration file './encounter.conf' is obsolete. The name will be converted into new format automatically if design is saved and then restored. Alternatively, update the configuration file to use names 'rda_Input(ui_preRoute_res)' and/or 'rda_Input(ui_postRoute_res)' for resistance scale factors to be used at preRoute/postRoute stages of the design . The obsolete name works in this release. But to avoid this warning and to ensure compatibility with future releases, update this option name.
**ERROR: (ENCSYT-16038):    'accu.vh' not found.

Loading Lef file /apps/FreePDK45/osu_soc/lib/files/gscl45nm.lef...
**WARN: (ENCLF-155):    ViaRule only supports routing/cut layer, but poly layer found for viaRule 'M1_POLY',
Set DBUPerIGU to M2 pitch 380.

Power Planner/ViaGen version 8.1.46 promoted on 02/17/2009.
viaInitial starts at Tue Oct 30 16:50:52 2012
viaInitial ends at Tue Oct 30 16:50:52 2012
**ERROR: (ENCSYT-16038):    'accu.vh' not found.
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.

*** Memory Usage v#1 (Current mem = 208.230M, initial mem = 46.070M) ***
*** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=208.2M) ***
**ERROR: (ENCSYC-300):    Cell accu not found.
**ERROR: (ENCVL-904):    Can't set top cell to "accu" because it doesn't exist.  Exiting Encounter!

*** Memory Usage v#1 (Current mem = 208.645M, initial mem = 46.070M) ***
--- Ending "Encounter" (totcpu=0:00:03.2, real=0:00:09.0, mem=208.6M)

 

Is this an installation problem/media problem or .tcl/.conf needs modification ? Thanks.

UG.

short circuit problems in P & R

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I'm using layer 3 and layer 4 for the power routing, so there are many vias through layer 3, layer 2 to layer 1.

Then there are some short circuit problems when some signals pass through the vias. Is there any option to avoid this kind of problems? Can't the tool detect these short problems and avoid these?

Thanks.


How to create vertical rows

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Hi , 

   Can anyone tell me how to create vertical rows,  in EDI

In user gude its written that "EDI can read database with veritical rows" but how to create them? in addtion its written that for vertical row's createRow command doesn't work .

I want to draw vertical follow pins .

 

Thanks

Nataraja G 

Hierarchical Flow

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Hi,

I have placed & routed design, and i want to import it to my top level.

i would like to know what is the recommended flow for hierarchical flow?

Thanks! 

using standard cells of multiple height

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I'm using the library cells from a particular vendor, but unfortunately a clock mux standard cell is not available with the particular vendor. But a clock mux standard cell for the same process and technology is available with another vendor. I have to use this particular clock mux from the second vendor and all other standard cells from the first vendor. But the Standard cell height of first vendor is 3.29 and that of the clock mux of the second vendor is 3.69. Please guide me how to solve this issue.

SDF Generation Confusion

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Hi,

I have been given some SDF that has been generated for min/max

write_sdf ../SDF/func.sdf      -precision 6 -max_view func_worst  -min_view func_best

 When I look in the SDF file, I see:

    (CELL
    (CELLTYPE  "SDFFRX1")
    (INSTANCE  instname)
      (DELAY
    (ABSOLUTE
    (IOPATH RN Q  () (0.445556::1.320084))
    (IOPATH RN QN  (0.282808::0.854712) ())
    (IOPATH (posedge CK) Q  (0.555220::1.656612) (0.407100::1.234008))
    (IOPATH (posedge CK) QN  (0.245180::0.769608) (0.303232::0.970056))
    )
      )
      (TIMINGCHECK
    (WIDTH (negedge RN) (::0.482700))
    (WIDTH (posedge CK) (::0.356600))
    (WIDTH (negedge CK) (::0.502200))
    (PERIOD (posedge CK) (::1.000000))
    (PERIOD (negedge CK) (::1.000000))
    (SETUPHOLD (posedge D) (posedge CK) (::0.351500) (-0.094300::))
    (SETUPHOLD (negedge D) (posedge CK) (::1.047800) (-0.297200::))
    (RECREM (posedge RN) (posedge CK) (::0.381600) (-0.049500::))
    (SETUPHOLD (posedge SE) (posedge CK) (::1.057100) (-0.088100::))
    (SETUPHOLD (negedge SE) (posedge CK) (::0.964600) (-0.146400::))
    (SETUPHOLD (posedge SI) (posedge CK) (::0.389800) (-0.107100::))
    (SETUPHOLD (negedge SI) (posedge CK) (::1.007200) (-0.292000::))
      )
  )

i.e. The MIN/MAX triplets are present for the IOPATHS, but for SETUPHOLD I see only max for setup and min for hold.

I think that this is giving problems in post layout gate level simulation (ncsim) where I use TOOL_CONTROL and +maxdelays. In this case, when I run a max simulation, no hold value will be annotated, so I see timing issues (since actual hold time is negative).

 I hope someone understands what I'm talking about ;-)

Can anyone provide a solution.

Thanks,

Steven

incomplete nets

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Hi all,

i am working with soc -encounter. while routing the design no violations were reported.
but when verified with calibre -lvs its showing 4 incomplete nets. when checked for same nets in soc - E those are no connected/routed as required.
what would be the reason & how to overcome such violations.

should these nets must be routed manually?

Thanks

A question about ELC(ex-SignalStorm)

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For the process statement definition in the setup file, the parameters like vtn and vtp are necessary? Does not the tool automatically get them through the model file? If they are necessary, where could I get them?

Thanks. 

a question about cell characterization

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how does ELC examine the syntax of input netlist?

Generating Reports

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Hi,

Where can i see what are the most important reports to generate after each step? (floorplan/placement/cts/routing/post rout)

Thanks! 

clockSpiceOut (an Encounter error)

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When I use Soc Encounter command "clockSpiceOut" to get the spice netlist form the clock tree, error happened like this:

"**ERROR: (ENCSPX-116): Cannot write subckt and model from encrypted CDB."

Why and what should I do?

Thanks very much.

Cadence Encounter doesn't fix hold violations?

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Hi everyone,
please help me with the next problem:

I'm designing a digital IC based on FPGA-verified source code using Cadence tools: Encounter for P&R and optimization and Incisive simulator (NCSim may be the second name) for checking the resulting waveforms.
After P&R, in post-route stage, I optimized design using the next commands:

optDesign -postRoute
optDesign -postRoute -hold

and the results are:
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.021 | -0.021 | 0.044 | N/A | N/A | N/A |
| TNS (ns):| -1.751 | -1.751 | 0.000 | N/A | N/A | N/A |
| Violating Paths:| 356 | 356 | 0 | N/A | N/A | N/A |
| All Paths:|3.64e+05 |2.45e+05 |1.19e+05 | N/A | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
+--------------------+---------+---------+---------+---------+---------+---------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 0.031 | 0.038 | 0.031 | N/A | N/A | N/A |
| TNS (ns):| 0.000 | 0.000 | 0.000 | N/A | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | N/A | N/A | N/A |
| All Paths:|3.64e+05 |2.45e+05 |1.19e+05 | N/A | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+

I know that setup violations were not fixed correctly, but hold were.
After that, I extracted the resulting netlist and SDF file and annotated them to simulator, and there are more timing violations in it's log file, but only HOLD. I think that setup violations were fixed decreasing the clock frequency in testbench, but, of course, HOLD not.

A part of ncsim.log file:
Warning! Timing violation
$setuphold<hold>( posedge CK &&& (ENABLE_RB === 1'b1):3236050 PS, negedge E &&& (ENABLE_RB === 1'b1):3236050 PS, 1.0 : 10 PS, 1.0 : 10 PS );
File: ./uk65lscsp10bbrccs_sdf30.v, line = 33170
Scope: :UUT.bis64.B_E.\tmp_reg[33] 
Time: 3236050 PS


Warning! Timing violation
$setuphold<hold>( posedge CK &&& (ENABLE_RB === 1'b1):3236050 PS, negedge E &&& (ENABLE_RB === 1'b1):3236050 PS, 1.0 : 10 PS, 1.0 : 10 PS );
File: ./uk65lscsp10bbrccs_sdf30.v, line = 33170
Scope: :UUT.bis64.B_E.\tmp_reg[34] 
Time: 3236050 PS

How can I fix hold violations in encounter? What I need to do? Please note, the program says that there are no hold violations in design.

Thanks in advance,
Kuxx.

FoundationFlow - what about floorplanning?

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Hi i have looked at the foundation flow scripts.

i didnt found anything regarding floorplanning, should  this step exists? or this flow starts from placement step?

Thanks. 

IMPORTING GDS

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Hi All, Can any one calify me the following concept: If i had a GDS file with me without having design data(i.e. design.enc format),is ti possible to import the design in encounter? If so ,explain the process with an example. KVB


Originally posted in cdnusers.org byviswanadhbabu
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