Hi All,
I have a design with many ram macros. We have created special SITEs for these macros in the floorPlan DEF. SITES are in coulumns of two macros side by side. The size of the the SITES is exactly same as the macros. If I let encounter do the placement. It was not honoring the SITE info for these macros and keep placing them all over. Is this the right way to do large number of macro placements??
Thanks,
Irfan
Hello!
I'm trying to connect vdd and vss nets to instance pins and the command
> globalNetConnect vdd_net -type pgpin -pin VDD_pin -inst instance_name -verbose
executes as expected and creates the connection. However, the command for vss connection
> globalNetConnect vss_net -type pgpin -pin VSS_pin -inst instance_name -verbose
returns the following message:
**ERROR: (ECNDB-1220): A global net connection rule for connection 'VSS_pin' of cell '...' to a global net '...' was specified. But the connection can not be made because the pin and the global net are not of the same polarity. Check the rule, and correct the issue.
I have examined the lef file of the instance to whose pin I want to connect the vss and the declaration of the pin (apart from USE GROUND vs. USE POWER) is exactly the same, both are 'INOUT'. I would love some suggestions on where to look for the polarity and how to resolve the problem.
The nets are analog power supplies comming from pins, through a clamp.
Hi,
i am getting the following error during placeDesign command:
the delay arc not on the source pin's list
does anyone know how can i debug this?
thanks!
Hi,
Can i open the gui after starting encounter with "encounter -nowin"?
Thanks.
Hi All,
I have a doubt regarding the contents contained in the captables.
What is the Exact difference between basic captable and Extended captable sections in the captable file.
Hi,
I am new to Encounter and Ramping Up...
I have cds.lib & libs.def in my working directory.
Does these files are imported automatically when i open the tool?
Many Thanks!
Hi,
I am trying the Hierarchical design flow, and just finished my macro block flow.
i have created power starps in my macro.
what is the best way to connect these power straps with top level power strips?
thanks!
Hi guys,
First,thanks for all your help with my recent questions.
I am trying to work with ILM in my top level, using cadence flow (i am not working in MCMM mode):
in my block level i do:
createInterfaceLogic -hold -dir ../outputs/my_block.ILM
the ILM created succesfully.
Than in top level, i write:
specifyIlm -cell my_block -dir ../outputs/my_block.ILM
and when i try placeDesign, i am getting n error that i didnt imported the ILM.
what am i doing wrong?
if I have multiple cells using this ILM should i run "specifyIlm" for each one?
Thanks!
When I try to add fillers in my design, there are some gaps between standard cells that can not add fillers into.
What may be the problems?
Thanks.
hi folks,
In my design there are 4000 flops. I need to sort them on the basis of endpoint slack value.
I wrote this script in encounter:
set paths [report_timing -collection -from [all_registers -clock_pins] -to [all_register -data_pins] -max_points 10000 -nworst 1]
set sorted_paths [sort_collection $paths slack]
This is sorting the paths but all instances are coming twice because of the pins SI and D. I need only one of the pin slack which ever is critical slack.
How can i filter my collection so that i get each flop only once.?
Hi All,
Iam working on cross talk analysis of mixedsignal design . and the SI analysis will do noise on delay and glitch noise analysis.
In my deisgn , the bits of bus are custuom routed and as per ETS tool , i dont have noise on delay issues. But , the tool shows glicth issues between the bus bits, i.e. it was shown that aggressors and victims are of same bus.
1) Can you suggest whether it can be waived off or not ?
2) I have gone through some paper which says , aggresors and victims of same bus are accounted for noise delay and does not effected due to noise on glicth. I did not understand this ? can any one share your taughts on this.
3) If it can be waived off , please share the reasons.
4) If they can not be waived off , pease suggest me some work around. Because, these bits of a bus from one macro to another
macro and there is no space also to increasing between the bus bits.
Regards,
K.VISWANADH BABU
my machine configure: Mem: 32908824k total, 20792292k used, 12116532k free, 78372k buffers
Swap: 8385920k total, 0k used, 8385920k free, 16006416k cached
when i optdesign , encounter crash out: report below :
*optDesign ... cpu = 1:01:13, real = 1:01:17, mem = 3370.9M **
*** Starting trialRoute (mem=3370.9M) ***
There are 0 pin guide points passed to trialRoute.
Options: -maxRouteLayer 5 -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 0
routingBox: (0 0) (16000000 14000000)
coreBox: (28000 28000) (15972000 13972000)
**ERROR: (SOCSYUTIL-15): Cannot malloc type "sysBigMacByte" size=227752272 bytes.
Probably ran out of virtual memory.
*** Memory Usage v0.144.6.3 (Current mem = 3462.359M, initial mem = 62.133M) ***
*** Memory Usage v0.144.6.3 (Current mem = 3462.359M, initial mem = 62.133M) ***
--- Ending "First Encounter" (totcpu=1:03:14, real=1:42:04, mem=3462.4M) ---
Hi,
I have read alot about this issue (in this forum), but still don't having some problems.
i have power strips + power ring in my block, and i use lefOut -stipePin in my block to generate the lef file for top level.
i can see in the lef file the power & ground port (also see "use power" & "use ground", and a list of "RECT" in top layer).
the problem is - i can't connect my top power strips to my macro block.
i use the "globallnetconnect" in my top level & in block level with the same names.
the thing is when openning my top level and reading the lef, i can see the block pins but not the VDD & VSS ones.
any idea?
thanks!!
When i do checkRoute..following message is seen
"several (1) nets have antennas or data inconsistencies
all 1074695 nets 4581405 terms of cell top_design are properly connected"
So can any one explain this........??
Hi,
After placing my hard macros using "planDesign" i am getting these colors over some of my hard macros:
what does it mean?
thanks!
Hi Bob & Kari
I did the following things,why the spef from "timeDesign -signoff -si" is different to the spef from "extractRC".
1. spef_01.spef.gz (one way)
setExtractRCMode -engine postRoute -effortLevel signoff -coupled true -lefTechFileMap qrc.layermap
timeDesign -signoff -si
so,the spef file "spef_01.spef.gz" will be extracted.
2. spef_02.spef.gz (another way)
setExtractRCMode -engine postRoute -effortLevel signoff -coupled true -lefTechFileMap qrc.layermap
extractRC
so,the spef file "spef_02.spef.gz" will be extracted.
but,why there are slight difference between "spef_01.spef.gz" and "spef_02.spef.gz" and which is more suitable to use?
Thanks advance!
Best Regards.
Hi,
for analysing the congestion after initial placement i have run trial route and it is showing
" overflow : 742 = 65 (0.00 % H) + 678 (0.05% V) ".( 65+678 = 743 ,, dont know why it is 742 ?)
But I am not seeing the congestion markers in the design display area to analyse where the problem is. I look for the visibility ON for all the options in the colour preference pallette.
can some one help me, whether i am missing something ?.
And please help me how to resolve this 742 nets overflow issue . any techniques/good practices ?
Thanks,
Sunil
Hi,
I am running Encounter with ILM blocks.
i have succesfully created the ILM and imported them to my top level.
However, after placement step ends, and i run timeDesign, i am getting "N/A" for all values in timeDesign summary table.
the sdc file is well defined and succesfully loaded at the beggining.
only after i run "flattenIlm" and resource the sdc file, i can see values in timeDesign table.
Help anyone??
Thanks!
Hi guys,
I'm using liberate to characterize standard cells which have a proprietary Transistor model, written in verilogA. Therefore I use spectre for simulation. First of all I wanna mention, that there is less guidance for how to set up another simulator than Aspice. Fortuneatly spectre gives also "*.mt0-Files" with the measurement results liberate expects. Unfortuneatly most of the liberate variables don't effect the temporary netlists in the expected way. So there is a lot of try and error.
Finally I gave up a wrote patches for the netlists with awk and sed.
So it runs fine and every step seems to get a "PASS" in the map.lst File. (I use customized arcs for speed and certainty). E.g.:
Jun 26 12:05:25 Thread 0: Cell=NOR2X1 (20%) Pin=QN Related=IN1 combinational rise_transition ...
Jun 26 12:13:27 Thread 0: Cell=NOR2X1 (40%) Pin=QN Related=IN2 combinational rise_transition ...
Jun 26 12:20:52 Thread 0: Cell=NOR2X1 (60%) Pin=QN Related=IN1 combinational fall_transition ...
Jun 26 12:28:46 Thread 0: Cell=NOR2X1 (80%) Pin=QN Related=IN2 combinational fall_transition ...
Jun 26 12:35:56 Thread 0: Cell=NOR2X1 (85%) Pin=IN1 Related= rising_edge rise_power ...
Jun 26 12:39:12 Thread 0: Cell=NOR2X1 (90%) Pin=IN1 Related= falling_edge fall_power ...
Jun 26 12:42:38 Thread 0: Cell=NOR2X1 (95%) Pin=IN2 Related= rising_edge rise_power ...
Jun 26 12:45:43 Thread 0: Cell=NOR2X1 (100%) Pin=IN2 Related= falling_edge fall_power ...
Jun 26 12:48:59 Thread 0: Cell=NOR2X1 (100%) Pin= Related= combinational leakage_power ...
Jun 26 12:49:08 Thread 0: Cell=NOR2X1 (100%) Pin= Related= combinational leakage_power ...
Jun 26 12:49:21 Thread 0: Cell=NOR2X1 (100%) Pin= Related= combinational leakage_power ...
Jun 26 12:49:31 Thread 0: Cell=NOR2X1 (100%) Pin= Related= combinational leakage_power ...
..But then
Performance statistics for NOR2X1: Spectre cpu time = 2521.2 seconds, total cpu time = 2521.2 seconds, wall clock time = 2668.0 seconds.
Error: cell NOR2X1 pin=QN related_pin=IN1 number of power results = 0, but 16 expected
Error: cell NOR2X1 pin=QN related_pin=IN2 number of power results = 0, but 16 expected
Error: cell NOR2X1 pin=QN related_pin=IN1 number of power results = 0, but 16 expected
Error: cell NOR2X1 pin=QN related_pin=IN2 number of power results = 0, but 16 expected
Error: cell NOR2X1 pin=IN1 related_pin= number of power results = 0, but 4 expected
However the "*.mt0-Files" give results for Leakage etc:
....altosleakage0 altosleakage1 temper alter#
2.959903e-09 3.905627e-09 27 1
I already scaled the values up but i looks like they will be ignored anyway. No idea why liberate don't get it. Until now I tried:
set_operating_condition -temp 27 -voltage 0.9
set VDD_voltage 0.9
set GND_voltage 0
set_vdd -type primary VDD1 ${VDD_voltage}
set_gnd -type primary GND1 ${GND_voltage}
set_var leakage_add_input_pin 1
set_var leakage_mode 1
set_var leakage_accuracy_mode 1
#set_var leakage_precision "%g"
set_var leakage_sim_duration "2e-12"
Nothing seems to help here. Please, Has anybody an idea?
Regards Eberhard
Hi All,
Is there any db command to find if any routes have gone outside the Die Area.
report/highlight those routes/nets.
Regards