Hi,
I've this warning in CTS (INNOVUS 17.15) but it is not specified in the documentation:
WARN: (IMPOPT-6253).
My question is: why the tool is not able to up-size the cell directly?
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WARN: (IMPOPT-6253): Wires for the net xxx have not been cut and moved to net yyy, because the added instance cannot drive all the necessary sink terms if the mentioned nets reuse the original routing.
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Best strategy to avoid incremental delay for long - coupled paths
Hi,
After Post Routing I've a lot of long - coupled paths, which results in setup violation due to the incr delay.
I've no problems of routing congestion or density, simply the tool (INNOVUS 17.15) doesn't recognize the cross talk issue.
What is the best strategy to avoid the problem?
Partial routing blockage?
Target-Based PostRoute Optimization ?
Thanks a lot
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Placing of physical design into another physical design in innovus
I want to place physical design of memory macros that I have created separately in another main design in innovus..
How to do that??
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Mixed signal Static Timing Analysis
Dear all,
I am working on a mixed signal design (analog on top) with custom analog and automatic digital implementation.
I would like to perform a static timing analysis including analog and digital. I have tried to follow the very good guide provided by https://support.cadence.com/apex/articleattachmentportal?id=a1Od0000007MJxdEAG&pageName=ArticleContent&attachId=069d0000003HOufAAG&sq=null, but I have issues assembling the design in Innovus which look to be related to the fact that the analog blocks have a "fully manual" layout.
Does anyone of you have experience in such scenario? If so, would you be so kind to share some documentation, flow, hint, suggestion?
On the other hand, I have found the following article on the Cadence blog, https://community.cadence.com/cadence_blogs_8/b/ms/posts/openaccess-oa-based-flow-key-to-enabling-efficient-implementation-of-mixed-signal-design-for-the-smart-devices-era. Does anyone know how to get the presentation/documentation related to it?
Thanks a lot in advance for any help/suggestion.
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RTL synthesis fault
Dear All,
While I am trying to synthesis from Verilog file with Genus, I find some faults. After I set my files, rest of my Tcl file is like at below.
elaborate
# Apply Constraints
set clock [define_clock -period ${delay} -name ${clkpin} [clock_ports]]
external_delay -input 0 -clock ${clkpin} [find / -port ports_in/*]
external_delay -output 0 -clock ${clkpin} [find / -port ports_out/*]
check_design -all
#Synthesis
synthesize -to_generic -eff medium
synthesize -to_mapped -eff medium -no_incr
synthesize -to_mapped -eff medium -incr
synthesize -to_mapped
#syn_gen
#syn_map
#syn_opt
#Reports
report timing > ./rep/${runDesign}_${delay}mHz_timing.rep
report gates > ./rep/${runDesign}_${delay}mHz_cell.rep
report power > ./rep/${runDesign}_${delay}mHz_power.rep
report area > ./rep/${runDesign}_${delay}mHz_area.rep
gui_show
When I use "synthesize ....." options under "#Synthesis", end of my log file as like below.
Info : Pre-processed datapath logic. [DPOPT-6]
: No pre-processing optimizations applied to datapath logic in 'pbs_gen_n_6'.
Info : Optimizing datapath logic. [DPOPT-1]
: Optimizing datapath logic in 'pbs_gen_n_6'.
Info : Implementing datapath configurations. [DPOPT-3]
: Implementing datapath configurations for 'CDN_DP_region_70'
Info : Done implementing datapath configurations. [DPOPT-4]
: Selected 'very_fast' configuration 4 for module 'CDN_DP_region_70'.
Optimizations applied to 'very_fast' configuration:
rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info : Implementing datapath configurations. [DPOPT-3]
: Implementing datapath configurations for 'CDN_DP_region_69'
Info : Done implementing datapath configurations. [DPOPT-4]
: Selected 'very_fast' configuration 4 for module 'CDN_DP_region_69'.
Optimizations applied to 'very_fast' configuration:
rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info : Implementing datapath configurations. [DPOPT-3]
: Implementing datapath configurations for 'CDN_DP_region_68'
Info : Done implementing datapath configurations. [DPOPT-4]
: Selected 'very_fast' configuration 4 for module 'CDN_DP_region_68'.
Optimizations applied to 'very_fast' configuration:
rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info : Implementing datapath configurations. [DPOPT-3]
: Implementing datapath configurations for 'CDN_DP_region'
Info : Done implementing datapath configurations. [DPOPT-4]
: Selected 'very_fast' configuration 4 for module 'CDN_DP_region'.
Optimizations applied to 'very_fast' configuration:
rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info : Done optimizing datapath logic. [DPOPT-2]
: Done optimizing datapath logic in 'pbs_gen_n_6'.
Removing temporary intermediate hierarchies under pbs_gen_n_6
Sourcing './.pbs_server.xx_177790/pbs_gen_n_6.etf' (Wed Jan 16 18:58:25 +03 2019)...
rdbfname wdbfname effort physical pas design assembly_index
./.pbs_server.xx_177790/pbs_gen_n_6.db ./.pbs_server.xx_177790/pbs_gen_n_6_post.db medium 0 0 /designs/pbs_gen_n_6 -1
Segmentation Fault accessing address ffffffffffffc6a0.
Fatal internal error, code 11 (Segmentation fault)
Dumping stack trace (tid:7fbce9466400/main thread).
Operating System: linux
Product Version:
Build Date:
Executable: /cds/GENUS171/tools.lnx86/synth/bin/64bit/genus
Startup Options: -legacy_ui
Current Directory: /home/user/work/genus/
Stack trace:
Segmentation fault (core dumped)
When I use "syn_gen ....." options, end of my log file as like below.
Info : Pre-processed datapath logic. [DPOPT-6]
: No pre-processing optimizations applied to datapath logic in 'pbs_gen_n_6'.
Info : Optimizing datapath logic. [DPOPT-1]
: Optimizing datapath logic in 'pbs_gen_n_6'.
Info : Implementing datapath configurations. [DPOPT-3]
: Implementing datapath configurations for 'CDN_DP_region_70'
Info : Done implementing datapath configurations. [DPOPT-4]
: Selected 'very_fast' configuration 4 for module 'CDN_DP_region_70'.
Optimizations applied to 'very_fast' configuration:
rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info : Implementing datapath configurations. [DPOPT-3]
: Implementing datapath configurations for 'CDN_DP_region_69'
Info : Done implementing datapath configurations. [DPOPT-4]
: Selected 'very_fast' configuration 4 for module 'CDN_DP_region_69'.
Optimizations applied to 'very_fast' configuration:
rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info : Implementing datapath configurations. [DPOPT-3]
: Implementing datapath configurations for 'CDN_DP_region_68'
Info : Done implementing datapath configurations. [DPOPT-4]
: Selected 'very_fast' configuration 4 for module 'CDN_DP_region_68'.
Optimizations applied to 'very_fast' configuration:
rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info : Implementing datapath configurations. [DPOPT-3]
: Implementing datapath configurations for 'CDN_DP_region'
Info : Done implementing datapath configurations. [DPOPT-4]
: Selected 'very_fast' configuration 4 for module 'CDN_DP_region'.
Optimizations applied to 'very_fast' configuration:
rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info : Done optimizing datapath logic. [DPOPT-2]
: Done optimizing datapath logic in 'pbs_gen_n_6'.
Removing temporary intermediate hierarchies under pbs_gen_n_6
Sourcing './.pbs_server.xxx_181030/pbs_gen_n_6.etf' (Wed Jan 16 19:44:50 +03 2019)...
rdbfname wdbfname effort physical pas design assembly_index
./.pbs_server.xxx_181030/pbs_gen_n_6.db ./.pbs_server.xxx_181030/pbs_gen_n_6_post.db medium 0 0 /designs/pbs_gen_n_6 -1
Illegal instruction (core dumped)
They are pretty much same but I just want to share. If you have any idea about it, it will be so helpfull for me.
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how to donwload youtube videos
Hello, There
how to donwload youtube videos?
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TCL command substitution seems to be broken in Innovus
commands that return a collection in Innovus (e.g. get_pins, get_ports, etc.) when used in TCL command substitution return a random hex value (handle to the collection maybe?) instead of the actual command results.
example:
innovus 32> get_pins u_atc_osctest/en_sync/*/*/CP
u_atc_osctest/en_sync/delay_line[0]_ff_pos_u_sync_ff_pos/u_endura_SDFSYNCND2/CP u_atc_osctest/en_sync/delay_line[1]_ff_pos_u_sync_ff_pos/u_endura_SDFSYNCND2/CP
0xa6a
The get_pins command correctly returns the pin names I wanted from my design (good!) and also some garbage hex value (bad). The hex # increments by 1 for every command I run that returns a collection.
If I try to use the results using the normal tcl sqare-brackets command substitution
innovus 34> create_ccopt_skew_group -name SG_test -sources [get_pins {u_atc_osctest/en_sync/*/*/CP}]
**ERROR: (IMPCCOPT-2057): Source '0xa6b' for skew group 'SG_test' is not a pin.
It passes the garbage hex value to the command, instead of the actual results. Note it does not matter what command I pass things to.
innovus 35> set test_list [get_pins {u_atc_osctest/en_sync/*/*/CP}]
0xa6c
innovus 36> echo $test_list
0xa6c
innovus 37> set test_list [get_pins u_atc_osctest/en_sync/*/*/CP]
0xa6d
innovus 38> echo $test_list
0xa6d
I always get the hex value instead of the actual command result.
This cannot possibly be a behavior that someone actually wanted.
Does anyone know why this happens, and how to make it stop so I can do TCL scripting in a normal way for Innovus. Thanks.
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Power estimation - Genus
Hello,
I am using Genus for post-synthesis power estimation, this estimation is based on the use of the lp_asserted_toggle rates and static probability.
The idea is I am wondering due to some results when i used the lp_computed toggle rates and static probability, because
When I build a 8 bit register like 8 DFF flip flops with an asserted clock frequency of 100MHZ (toggle rates=0.2 and static probability=0.5) with inputs asserted to taoggle rates that exceed 0.1 (more than f/2)
I get at the output of the flip flops toggle rates as the inputs for example for 0.15 i got 0.15 for the output, classically the flip flop should suppress the effect of glitch (cases where toggle_rates >0.1 in our case)
I kindly ask you to help to understand this issue well.
Best Regards,
Yenass
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Low power design - Power estimations Genus - Toggle rates and static probability
Hello,
I have a problem when I used the lp_computed toggle rates and static probability, when I built an 8 bit register like 8 DFF flip flops with an asserted clock frequency of 100MHZ (toggle rates=0.2 and static probability=0.5), and the problem that I did not understand when the data inputs are with inputs asserted_toggle_rates that exceed 0.1 (more than f/2), and I got at the output of the flip flops toggle rates as the inputs, for example if 0.15 asserted toggle rates, I got 0.15 for the output, classically the flip flop should suppress the effect of glitch (cases where toggle_rates > 0.1 in our case).
Noting that, by definition: toggle rates of a clock signal is = 2*(1/T) , where T is the period in ns and 2 means 2 toggles within T (source: cadence RTL-Compiler reference guide), for a data signal at the input of a flip flop, a signal with activity factor of 1 like a clock signal toggles 2 times within 2*T so the toggle rates maximum without glitch is equal to 2/2*T=0.1 for this purpose any value of 0.1 toggle rates represent a data signal that toggles each T, so for this purpose numbers greater than 0.1 and less than 0.2 should be suppressed by a flip flop by theory, but is not the case with the tools and simulations. Note that also, putting values greater than 0.2 at the input of a flip flops gave a maximum of 0.2 at the outputs.
Thanks to help to understand why the tools gave this results.
Regards,
Yenass.
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Multi bit FF flop scan enable tied on
Hi all,
after place, (INNOVUS 17.15) I've a report for Multi bit FF.
Many flops are not merged because "Nonremovable single-bit flip-flop: scan enable tied on".
I don't understand why a flop with scan en. tied on can't be merged with other SE tied on flops.
Can you help me?
Thanks
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How to provent double extract parasitic cap use EXT tools!
Hi,guys!
I want use EXT16 tools to extract parasitic.
When I create qrtTechFile use ICT file,I find the Techgen -compilation cmd has a option -cap_correction can subtracts calculated plate-to-plate capacitance from the parasitic capacitance between the two nets of a canonical capacitor,but it does not work on finger CAP(like mimcap) devices in RC extraction mode.
Now, I want subtract the finger CAP too in RC extraction mode,how can i do?
Any help are best !
Best regards!
Gong
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Power consumption per clock cycle using Genus
Hello there!
Using Genus, is there any way to have, in addition to leakage and dynamic power consumption, also the power consumed per clock cycle in the power report?
For example, I have to calculate the power consumed by a synchronous adder for an entire addition on 32 bits...how could I do?
Thank you in advance.
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Floorplanning and scripting problems
Hello,
I am running into some problems with the floorplanning of my design. My script basically consists of:
1- Change the floorplan size for a given density specification
2- Ungroup the top module, and place some sub-modules in my design at particular locations
The thing is when I run my script, the floorplan size is changed but not the density of the top module (which stays at 70%). To have it changed, I need to ungroup the top module by hand so the changes are applied.
How to automatize this in my script? If I ungroup the module in my script, it does not work as well, I still somehow need to do it by hand.
Am I missing something?
Thanks.
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setPlaceMode -place_global_sdp_alignment & place_global_soft_guide_strength
Hi
I just found out that when I set
setPlaceMode -place_global_sdp_alignment true
or
setPlaceMode -place_global_soft_guide_strength high
I got different placements even though I didn't put any constraint (soft guides) and no sdp file applied.
As checking floorplan file, there's no module guides:
#####################################################################
# Fence: <name> <llx> <lly> <urx> <ury> <nrConstraintBox> #
# ConstraintBox: <llx> <lly> <urx> <ury> #
# ... #
# Region: <name> <llx> <lly> <urx> <ury> <nrConstraintBox> #
# ConstraintBox: <llx> <lly> <urx> <ury> #
# ... #
# Guide: <name> <llx> <lly> <urx> <ury> <nrConstraintBox> #
# ConstraintBox: <llx> <lly> <urx> <ury> #
# ... #
# SoftGuide: <name> #
# ... #
#####################################################################
I wonder how these two settings affect a placement.
Thank you in advance.
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How to set a DRC for diff pairs
I how do I adjust my constraints so that when I set a primary gap for a diff pair and my diff pair is not within that limit it gives me a DRC? Wasn't sure if this is an easy to answer question but any help would be great.
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place and route using INNOVUS
Hi,
I have made my standard cell library and used genus fo synthesize and now I am trying to do place and route using Innovus.
But I get this error from Innovus" ERROR (LEFPARS-1509): PITCH statement is a required statement in a LAYER with type ROUTING and it is not defined"
"ERROR (LEFPARS-1510): WIDTH statement is a required statement in a LAYER with type ROUTING and it is not defined."
and I check the .lef file which I get from Abstract generator and the pitch and width statement are defined already.
Does anyone know why I get this error, and how to fix it? Thanks.
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PVS unavailable using Innovus
The menu PVS is unavailable (grayed out) at Innovus. I'm using INNOVUS 18.10 and PVS 16.12 and I tried to modify the script so that the PVS path come before or after Innovus path and in neither those cases worked. How to fix this?
This is a sample of my script:
export INNOVUS=$CADENCE/INNOVUS181
export PATH=$INNOVUS/bin:$INNOVUS/tools/bin:$PATH
export PVS=$CADENCE/PVS161
export PATH=$PVS/bin:$PVS/tools/bin:$PATH
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constraints file
Could any one please help me how to find the post layout delay of a full adder circuit?
I am working with digital cadence and when i try to get the post layout delay, the report is shown as "NO CONSTRAINED TIMING PATHS FOUND"
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Integration of MATLAB with Cadence for Image Processing
Dear Technical Team,
I wish to have clarification and support from cadence on the following.
1.I wish to know list of features that can be integrated with matlab.
2. Can cadence be integrated with simulink ?
3. Is there any possibility to use image processing tool box to feed input
to the digital circuit designed through virtuoso ?
4.does post layout simulation process after extracting parasitic and
including it to schematic supports matlab?
5.Is there any document which gives step by step procedure for integrating
all the features of two tools (CADENCE + MATLAB)?
Please, facilitate me with the sufficient materials so that I can realize
and benefit from the fruitful integration of two companies tools
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MBIST
Hi
I am trying to implement address decoder open test for purpose of memory testing,i have got the algorithm but in the paper it is not properly mentioned how to exactly implement the algorithm.
I got the algorithm to implement MARCH test and Checkerboard but in implementing address decoder open test i am facing issue.
Can I get a help please?
Thanks
Himanshu
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