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multiple and indepedent clock in the same circuits

March 6, 2019, 7:46 am
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Hi there,

I wonder if that would be possible to synthesize a circuit with multiple
and independent clock in the same circuit. the circuit is made of the
following items:
+ 32 independent full custom oscillators, each one providing its output
signal as a clock for the next stage
+ 32 independent counters which take as a clock the output of one of the
oscillators mentioned above
+ 1 readout circuit with its own clock that is only working when the
counters are not counting.

The system work as follow. A signal allow all the counters to count
with a clock signal coming from a full custom oscillator. The
oscillation frequency for each oscillator is different because they're
not made the same way and this oscillation frequency may vary according
to temperature, or aging, or some other parameters. Because we know how
long the counting gate has been opened, we can use this device as a
monitor for the parameters of interest. Once the counting gate is
closed, we need to get the value of the counters. for this we use the
readout circuit which has its own (low) clock frequency.

Also, I would like to be able to run the placement in innovus with each
counter being a device of its own and the readout being a cell of it own
too. the small sketch below show exactly what I intend to do.

Thank you for your time and consideration.

Olivier

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Power Consumption in Genus and Spectre

March 11, 2019, 3:54 am
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Hello everybody!
I'm facing a problem using the aforementioned software: basically I implemented a circuit in HDL and synthesized it, reporting its power report, which indicates a power consumption of hundreds of nW. Than I simulated the netlist in Spectre, and the power consumption differs of a 1000 order of magnitude (uW vs the previous nW). 
Now, I did not expect the two values being the same, since Spectre should be more accurate, but at least not that far from each other.


Somebody having some explanation for this?

Thanks in advance.

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Encounter Test: switch from command line mode to GUI

December 11, 2018, 3:28 pm
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Hi,

After building test mode in command line, I would like to analyze the inactive logic in ET tools GUI.

How to switch from command line mode to GUI  from with in the same tcl script?

Regards,
Venkat

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Issue on place_connected INNOVUS 18.12

March 21, 2019, 6:34 am
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Hi,

I'm trying the following:

set attractorpin {*/D */Q}

place_connected -sequential direct_connected -attractor_pin $attractorpin -attractor $BlockPins -placed

I'd like only inst/D or inst/Q attracted by BlockPins, but I find in the log:

Instance 'xxx/pippo', term 'SI' is counted in as attracted

Instance 'xxx/pippo', term 'CP' is counted in as attracted

Instance 'xxx/pippo', term 'SE' is counted in as attracted

Why?

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Genus 18.1 cannot resolve compiled, hardmacro, memories

March 25, 2019, 10:34 am
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All the .libs and the .lefs for the memories are being read in ok.  But when it comes to elaboration, Genus says it cannot resolve the memory.  No other suspicious messages about the mems.  Can somebody please throw some clues/pointers my way?

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Power Analysis Warnings

March 26, 2019, 3:14 am
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Dear All,

I am running power analysis uing Innovus and getting following warnings during the run:

** WARN:  (VOLTUS_POWR-2047): The following cell(s) power_level cannot be mapped. Check if the connections of the power/ground pin to the external rails have been specified. The power will be distributed to the default rail.

 

POWER LEVEL         CELL                              INSTANCE

CORE_VOLTAGE        PDIDGZ                            Pad_clk

IO_VOLTAGE          PDO02CDG                          Pad_dc

 

** WARN:  (VOLTUS_POWR-2041): There are some instances in the design which are not connected to any power or ground nets.

These instances will be added to default power/ground rail uti files.

Use 'itaputil list <uti-file>' command to get the list of instances.

The cells reported in the warnings are IO cells which I've instantiated in my netlist and no warning appears during sroute before the power analysis. Could anyone please help me in resolving these warnings?

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April 10, 2019, 6:13 am
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solidwooddiningtable (.) co (.) uk

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Systemverilog interfaces over hierarchical boundaries

December 13, 2018, 6:50 am
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I have experienced some back-end issues using systemverilog interfaces when and interface is traversing over hierarchical boundaries. I've tried to sketch the situation in the attached drawing.

The top picture shows the "regular" method of using interfaces. the interface and connected module are all instantiated at the same level of hierarchy. This works for simulation and back-end.

The middle picture shows my situation. At the toplevel I have a module and interface instantiation. The interface is connected to the purple module and then connected to 2 sub-modules. In simulation this works.

Then the synthesis tool complains that the interface at the purple level should be an modport. So I added that. However the synthesis tool is interpreting the wires in the as bidirectional and adds logic to facilitate this. In my design all wires are unidirectional.

The only workaround I could find to fix this issue is depicted in the lower picture. I connect via a modport the original interface (labeled A). Then I instantiate a new interface (labeled B) which has the same parent as interface A. Both interfaces A and B are connected to a connect module which contains a lot of statements like:

assign interfaceB.rx1 = interfaceA.rx1;

assign interfaceB.rx2 = interfaceA.rx2;

assign interfaceA.statusX = interfaceB.statusX;

etc

so it is just a "dumb" connection of interface A and B.

This way of work feels very wrong as this connect module is creating a lot of overhead. Is there a good / easier way of using the interface over hierarchical boundaries that is not only working in simulations but also works for synthesis?

Thanks

community.cadence.com/.../3817.drawing.pdf

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Inport .spef file in Spectre

May 1, 2019, 2:28 am
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Hello there! 
I would like to know whether (and in case how) it is possible to include into the spectre circuit netlist the .spef file, generated after the P&R, in order to simulate the circuit also with the parasitic Rs and Cs.

Thank you in advance.

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DELAY OF PARTICULAR PATH

May 2, 2019, 12:31 am
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I am dealing with design of multi bit adder. I am using the command 'report_timing -unconstrained' to calculate the delay of the design. This command is giving the delay of the critical path in the design. What is the command to be used inorder to get the delay of a particular input to output path, other than the critical path?

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Missing Power Pins in .dspf File (Cadence Innovus)

May 9, 2019, 3:13 pm
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Hi,

I hope this question is more relevant to this forum than Custom IC. I am trying to perform transistor level post layout simulation on a 'P&R'ed digital design. After P&R and timing optimizations, I import the post layout netlist (without physical only cells) to Virtuoso along with extracted .dspf file. I have the OA version of the reference standard cell library in Virtuoso in which all cell views have power and well contacts. However the .dspf from Innovus does not have these contacts in "instance" section, so that when the .dspf is annotated to the schematic netlist, spectre simulation stops throwing following error :

ERROR (SFE-45): `Xpipe_in_0__dxin': An instance of `DFQBRM1RA' needs at least 8 terminals (but has only 4). 

The schematic Netlist looks like below:

subckt ND2M1R Z A B VDD VSS VBN VBP
M0 (N_8_M0_d B VSS VBN) n_12_llrvt l=6E-08 w=3E-07 sa=1.75E-07 \
sb=3.95E-07 nf=1 mis_flag=1 sd=200n as=5.25E-14 ad=2.4E-14 \
ps=9.5E-07 pd=4.6E-07 sca=21.1826 scb=0.0232952 scc=0.00281296 m=1 \
mf=1
M1 (Z A N_8_M0_d VBN) n_12_llrvt l=6E-08 w=3E-07 sa=3.95E-07 \
sb=1.75E-07 nf=1 mis_flag=1 sd=200n as=2.4E-14 ad=5.25E-14 \
ps=4.6E-07 pd=9.5E-07 sca=21.1826 scb=0.0232952 scc=0.00281296 m=1 \
mf=1
M2 (VDD B Z VBP) p_12_llrvt l=6E-08 w=4.5E-07 sa=1.75E-07 sb=4.35E-07 \
nf=1 mis_flag=1 sd=200n as=7.875E-14 ad=4.5E-14 ps=1.25E-06 \
pd=6.5E-07 sca=57.4294 scb=0.0457325 scc=0.00629633 m=1 mf=1
M3 (Z A VDD VBP) p_12_llrvt l=6E-08 w=4.5E-07 sa=4.35E-07 sb=1.75E-07 \
nf=1 mis_flag=1 sd=200n as=4.5E-14 ad=7.875E-14 ps=6.5E-07 \
pd=1.25E-06 sca=53.2271 scb=0.0383044 scc=0.00577594 m=1 mf=1
x_PM_ND2M1R\%B (B) _sub6
x_PM_ND2M1R\%A (A) _sub7
x_PM_ND2M1R\%VSS (VSS) _sub8
x_PM_ND2M1R\%Z (Z) _sub9
x_PM_ND2M1R\%VDD (VDD) _sub10
x_PM_ND2M1R\%VBN (VBN) _sub11
x_PM_ND2M1R\%VBP (VBP) _sub12
x_PM_ND2M1R\%8 (N_8_M0_d) _sub13
ends ND2M1R

whereas .dspf : 

Xtest\/cla1\/U27 test\/cla1\/U27:A test\/cla1\/U27:B test\/cla1\/U27:Z ND2M1R

Is possible to include these pins when .dspf is extracted ? Or  is there a workaround to bypass this in Virtuoso ?

My extraction settings in Innovus look like this :

setExtractRCMode -engine postRoute -effortLevel high
extractRC

mkdir TC/
rcOut -setload TC/${DESIGN_NAME}_tc.setload -rc_corner rc_tc
rcOut -setres TC/${DESIGN_NAME}_tc.setres -rc_corner rc_tc
rcOut -spf TC/${DESIGN_NAME}_tc.spf -rc_corner rc_tc
rcOut -spef TC/${DESIGN_NAME}t_tc.spef -rc_corner rc_tc
write_sdf -view data_gen_tc TC/${DESIGN_NAME}_tc.sdf

 Thanks in advance

Anuradha

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WARN: (IMPOPT-6253): Wires for the net xxx have not been cut and moved to net yyy, because the added instance cannot drive all the necessary sink terms if the mentioned nets reuse the original routing.

December 17, 2018, 12:18 am
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Hi,

I've this warning in CTS (INNOVUS 17.15) but it is not specified in the documentation:

WARN: (IMPOPT-6253).

My question is: why the tool is not able to up-size the cell directly?

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Chip Utilization with Innovus

May 13, 2019, 2:50 pm
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Hello to everybody!
Right now I'm facing a problem with the place and route of some adders: in fact, I would need to optimize the floorplan area, and so I would have to have the maximum chip utilization % possible.

However, I thought about a tcl script, but I do not know how to save the core utilization of a particular combination of H/W ration and utilization. 
The only thing I can do is to use 

checkFPlan -reportUtil

but this only shows the data I want to save in a variable.

Do you know how can I do this?

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Innovus Parasitic Extraction Compatible for Spice Simulation

May 14, 2019, 1:19 pm
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Hi All,

Is it possible to annotate the interconnect parasitics (.spef and .dspf) generated (IQRC) after P&R in Innovus,  with a pre-layout transistor level netlist of standard cells in Virtuoso ? This procedure is bit similar to post-layout STA. Instead of gate level netlist, I wonder whether we can use the interconnect parasitics with transistor level netlist. Instead of doing GDS flow, can we generate accurate timing and power numbers in this way ? 

Ranayas

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Metal fills after Routing

May 28, 2019, 2:15 am
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Why the software avoids adding the metal fill near the clock and signal nets and adds more near the power and ground nets.

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How to add custom menu in Innovus

May 28, 2019, 9:44 am
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Hi,

I have few custom checks which i need to add as a menu button in Innovus gui window. Is that possible? 

Please let me know the process.

Thanks.

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Irun: Continue on error

June 11, 2019, 11:15 am
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Hey,

We are using irun for compilation and elaboration of our design. Is there a switch that can be used to continue on elaboration errors, so that we can get all errors at once. We are re-using our design from previous project and initial elaborations fails finding required instance definitions. It will be great if we can get a switch to display all errors at once, so that we can fix them in one go. Example error:

xmelab: *E,CUVMUR (<some verilog file>,210|33): instance 'abc.xyz_inst' of design unit 'xyz' is unresolved in 'worklib.abc:v'.

Thanks,

Abhishek

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D Flip-Flop with asynchronous reset characterization using Cadence Liberate

June 12, 2019, 7:37 am
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Hi ,
 
I am developing standard-library for technoloyg with few cells: NAND, NOR, NOT, LATCH, D Flip-Flop and D Flip-Flop with asynchronous reset. I am able to synthesize all cells except for the D Flip-Flop with asynchronous reset. I have simulated the design using spectre simulation and the functionality is correct.
I see no errors during the synthesis flow only some warning regarding the undefined templates for constraints. 
My cell definition is as follows:
if {[ALAPI_active_cell "DFFNRX1"]} {
define_cell \
-clock { CP } \
-async { RST_N } \
-input { D } \
-output { Q Q_bar } \
-pinlist { CP D Q Q_bar RST_N } \
-delay delay_3x3 \
-power power_3x3 \
DFFNRX1

}
 
At the end of characterization, tool shows the warning:
*Warning* (write_verilog) : No function written for pin Q of cell DFFNRX1
*Warning* (write_verilog) : No function written for pin Q_bar of cell DFFNRX1
also in the .lib file I don't see the function for the Q and Q_bar. Could anyone help me?
Thanks
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Metal Fill within Innovus in N5 TSMC technology

June 17, 2019, 7:46 am
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Hi all,

I'm trying to generate metal fill after finishing detailed routing in order mainly to utilize empty area to add more power strapping but no matter what I do the Innovus does not generate metal fill at all without giving me any clear reasons or errors why.

Does anyone know how to make this work?

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How to clock gate in hierarchy?

June 18, 2019, 2:37 am
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Hi,

I am trying to clock gate a part of my design with one enable signal. It seems logical to me that instead of using the enable signal to each register inside the modules and sub-modules, it would be better to directly gate the clock high in the hierarchy.
I would like to use the special clock gating cell from the std cell library and not the generic latches and gates. Is there a way to infer the clock gating to the synthesis tools?
Is there something similar to the ChipWare library, for example, that can infer clock gating cells?

Best Regards,
Dimitrios

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