Hi
I am using INNOVUS for P&R my design. In each run of place and routing some short circuit violations are observed on Metal1 after running geometry verification. The location of the violations change in each run of generating the layout. I wonder if anybody can help me to solve this problem.
Thanks in advanced.
Ati
Hi,
When I import the top level Verilog file generated by Genus into Virtuoso, the power pins are left unconnected. I tried different configurations in "Global Net Options" tab. However, nothing changed.
The cell is imported with three views, namely functional, schematic, and symbol. In functional view everything looks OK, that is the top level Verilog file. In schematic, I can see the digital cells but VDD and VSS pins of the blocks are not connected. In the symbol view there are no pins for VDD and VSS.
On top, we are trying to implement a digital block into Virtuoso. The technology is TSMC 65nm. On Genus and Innovus, everything goes straight and layout is generated successfully.
Thanks.
Bora
Hi,
I use genus to synthetise my digital design and create verilog and sdc files.
Then i importe my mmmc.tcl file into my innovus workflow the consol say : cannot open SDC file '../genus/results/SHM_ASIC_TL.sdc' for mode 'typical_constraint'.
The file SHM_ASIC_TL.sdc is created directly from synthesis and had the right name!
By mmmc.tcl file i call the sdc file as: bellow
create_constraint_mode -name typical_constraint -sdc_files {SHM_ASIC_TL.sdc}
but it's doesn't work..
Has somebody an issus?
Thanks a lot, Vincent
Hi,
I use Innovus (P&R) multiple Vt libraries together.
Are the library settings correct below?
create_library_set -name LIBXX -timing {lvt.lib nvt.lib hvt.lib}
Placement is hvt.lib only.
I want to use (hvt.lib, nvt.lib, lvt.lib) all after Route.
Please tell me the script.
set_dont_use [get_lib_cell * nvt *] true
set_dont_use [get_lib_cell * lvt *] true
place_opt_design
:
set_dont_use [get_lib_cell * nvt *] false
set_dont_use [get_lib_cell * lvt *] false
optDesign-postRoute
Best Regards,
SH ken
Best Regards,
SH ken
Hi,
I am new here in this forum.
May I know where can I get a tutorial on how to start Innovus?
I want to learn even the basic placement and routing even without any constraints just to get start with.
Thanks in advanced.
Hi community,
I'm actually designing an IP where i need to send a signal from (x1;y1) to (x2,y2) in the floorplan.
In the following, i explain how i'm actually handling with my design :
For the drivers and receivers i'm selecting 2 buffers from the timing library i'm using.
I can be brought to route the driver and the receiver in different routing metal layer (mainly i need the most top metal available)
to connect the buffer to the routing net i'm designing a custom pillar via.
The mesh line that route the buffer driver to the buffer receiver could have different length and width.
Today, to ensure that the signal arrive to the buffer receiver, i'm choosing by default the largest buffer for the driver (BUFF_V20, BUFF_V16, BUFF_V24 ....)
My biggest fear is to have EMIR issues if the mesh line that route the driver to the receiver is a long line (hundreds of um of length for example) and a small width (1,2or3 um of width)
My questions are the following :
- Do you have any characterisation method, that allow me to choose the right buffer drive for both buffer driver and buffer receiver?
- I started a brainstorming to find some solutions and here what i did now;
- in an empty floorplan i place amnually the different buffer available in my library to implement the drivers. i made a choice of one buffer to use it as a receiver and place them aligned
with the drivers.
- i route manually the drivers to the receivers on METAL layer 3
- i generate a spef file to do an annotated simulation with spectre.
this implementation do not allow me to figure out which buffer i should use since the current and voltage are perfect with the different set of drivers. (no voltage drop or current attenuation during propagation)
I will be grateful to have your feedback and advices.
Thank you.
--Erwan
I am wondering if I can read in the system verilog files in innovus
Hi Experts,
I am very new to physical design and have some questions regarding low power concepts.
1. What does CLP tool used for, Is it integrated with INNOVUS?
2. Why there is no command in INNOVUS to add_isolation_cells/add_level_shifters/add_retention_cells, what is the advantage of adding these commands in the UPF file?
3. Why there is a command to add_power_switch in INNOVUS, even when they are defined in UPF.
Please spare me some time to understand these concepts.
Thanks
Utkarsh
Is there a better approach to varying the coefficients of a digital IIR over time to adjust the values of its poles and zeros than just recalculating the whole thing every time it changes? For example, lots of synth programs can apply an LFO to the cutoff frequency of a low/high pass filter. I can do some polynomial multiplication to get the coefficients for an IIR filter given its poles and zeros, but am wondering if there is a better way to adjust them over time than simply doing all the calculations over again for new poles/zeros. Particularly, I'm curious if there is a method that will more or less work for an arbitrary number of poles and zeros. You could use a filter implementation (state space) that directly uses the pole/zero values instead of a polynomial. That might be computationally more expensive, though (as you are taking a trip through the domain of complex numbers even though your inputs and output are real), and possibly numerically iffy.As far as I am aware, modifying filter behavior while introducing as few artefacts as possible is still an area of research. You might get away with just adjusting the filter coefficients if you do it slowly, but this does not mean this is the best method.In an audio application, I assume they do not switch filter coefficients abruptly, but instead do a cross-fade between the (settled) first filter and the (mostly or completely settled) target filter to avoid audible artefacts.
Currently trying to plot the magnitude spectrum of a single tone FM modulated signal in Matlab. I made a small error where the modulating frequency (fm) was of the same order of ten as the carrier frequency (fc). For example, both were in the MHz range instead of having fm in the kHz. The magnitude spectrum I plotted when the mistake was present was great with multiple sidebands etc and what I expected. I picked up my error, corrected it and the plot changed to only showing one spike at fc. Why is this? It only seems to plot well when fc and fm are of the same order of ten.
This might be more of a Matlab question but I would love to know any theory behind it. :) Thanks
Hi All,
The below report is from timeDesign after placement. I see N/A in most of the columns. Due to this, no information is written to the timing reports and also couldn't able to analyze the timing impact of this stage. Apart from loading of constraints in the floor plan, I do load certain disable timing arc statements before the start of the placement with the following statements,
set_interactive_constraint_modes {mode_norm mode_scan}
source "constraints.tcl"
set_interactive_constraint_modes {}
Does anyone faced the similar issue before?
Hey there,
I see the term "digital transformation" thrown about quite a bit and can't really determine how this is different than running an information technology department... or "doing" IT.
It sounds like it means some combination of moving business processes to applications, collecting and analyzing data and providing technology for a company's customers. All of which sounds like a modern IT department to me.
Thoughts?
Guys,
So far I was working with Windows systems and ModelSim. But as a new task, I need to work with NCSim and Of course on Linux. I need to setup all tool chain. I simply don't know both of these things, and there is no one around to help.
So the questions are: How much Linux will be sufficient and how to start learning NCSim, as on net, there are very very few tutorials are available.
Any link and suggestion is warmly welcome.
I how do I adjust my constraints so that when I set a primary gap for a diff pair and my diff pair is not within that limit it gives me a DRC? Wasn't sure if this is an easy to answer question but any help would be great. Distance
Hello everyone,
I am currently adapting Voltus-Fi to the design flow (UMC180 technology).
The EM/IR analysis through ADE-L seems to work (judging by changing the output plots).
But displaying Results > EM/IR Data > Layout Analysis with choosing IR-drops for the nets (say AVDD) fails, since vpserro layers are not displayed on the layout view (although these layers are visible in the Palette tab and in the IR/EM Results window min and max values are as well specified and differs through various nets).
Have you any ideas how to deal with this problem?
Regards,
Artur
Hi,
I have a stdcell library which has “.v” file which contains all Verilog models for stdcells. This stdcell library also has a “.lib” timing file with all the delay information for these verilog stdcells. This ".lib" has been provided to us by stdcell IP vendor.
Could you guide me how can I use this “.lib” timing file inside Virtuoso AMS simulation using ADE?
Do I need to convert this ".lib" file into SDF? If yes, how?
Could you also point me to the right documentation if available?
Thanks in advance.
Dear all,
I'm struggling with an issue about PnR with Cadence Innovus 16.22 .
I would like to "force" the tool to make routing between power nets vdd/gnd and well taps' contacts vdds/gnds. See picture for details.
Please, can anyone give me some advice to accomplish the task?
Kind regards,
Tonio
Hello.
I would like to ask for help.
I'm using EDI(v14), some layer name is different between captable and tech lef.
For example,
in captable : Metal1, M12C, Metal2, M23C, Metal3, ...
in tech lef file : M1, V1, M2, V2, M3 ....
Will EDI automatically recognize each as the same layer?
I found some glitch filter design on the internet but I am unsure of how to set a typical value for the the glitch delay.
Assume the clock speed is 800MHz on a die of 3*3mm at 28nm. How should one decide for that delay?
Thank you in advance.
I have a clock gating latch cell (latch_posedge_precontrol) that has a statetable that Genus complains about:
statetable ("CLK GATE RESETB", "int_m0") {
table : " L L H : - : L ,\
L H H : - : H ,\
H - H : - : N ,\
- - L : - : L ";
}
It says
The clock-gating integrated cell 'scc9gena_gltp_1' is not usable because state table has incompatible entry in row '4' for 'CLK' column.
Warning : The clock gating integrated cell has no state table or latch group definition. [LBR-102]
Changed it to make CLK a more explicit H or L:
statetable ("CLK GATE RESETB", "int_m0") {
table : " L L H : - : L ,\
L H H : - : H ,\
H - H : - : N ,\
L - L : - : L ,\
H - L : - : L ";
}
That moves the complaint down a line:
The clock-gating integrated cell 'scc9gena_gltp_1' is not usable because state table has incompatible entry in row '5' for 'CLK' column.
Warning : The clock gating integrated cell has no state table or latch group definition. [LBR-102]
: The 'scc9gena_gltp_1' has no state table or latch group definition.
What is Genus looking for in the statetable?
Thanks
Kevin K