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Extract logic cells from design to match cells provided by pdk?

October 7, 2019, 3:00 pm
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Hello,

I'm completely new to this so please bear with me.

If I'm provided with some standard cells, and would like to use a design that I have in an FPGA to port to an ASIC using the provided cells, how do I determine which of the provided cells I will need? Is there a way to get from the RTL or FPGA design the logic cells that I can use in an ASIC? The library I have with the standard cells has multiple logic cells for the same function (multiple nands, nors, etc.), so how would I know which ones my design will translate into?

Thanks!

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DRC ERRROR

October 16, 2019, 7:04 pm
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How to fix these DRC errors which is shown in the following image.

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Luxury Hotel in Delhi- Hotel Atithi Palace

October 18, 2019, 12:18 am
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D Flip-Flop with asynchronous reset characterization using Cadence Liberate

June 12, 2019, 7:37 am
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Hi ,
 
I am developing standard-library for technoloyg with few cells: NAND, NOR, NOT, LATCH, D Flip-Flop and D Flip-Flop with asynchronous reset. I am able to synthesize all cells except for the D Flip-Flop with asynchronous reset. I have simulated the design using spectre simulation and the functionality is correct.
I see no errors during the synthesis flow only some warning regarding the undefined templates for constraints. 
My cell definition is as follows:
if {[ALAPI_active_cell "DFFNRX1"]} {
define_cell \
-clock { CP } \
-async { RST_N } \
-input { D } \
-output { Q Q_bar } \
-pinlist { CP D Q Q_bar RST_N } \
-delay delay_3x3 \
-power power_3x3 \
DFFNRX1

}
 
At the end of characterization, tool shows the warning:
*Warning* (write_verilog) : No function written for pin Q of cell DFFNRX1
*Warning* (write_verilog) : No function written for pin Q_bar of cell DFFNRX1
also in the .lib file I don't see the function for the Q and Q_bar. Could anyone help me?
Thanks
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CreateSnapshot for an exact bbox

October 24, 2019, 8:17 pm
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How can i write out an image for exact bbox size? currently i see innovus wirtes out snapshot of the entire layout view area. 

Thanks

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Varying a digital IIR filter's poles&zeros over time

November 11, 2019, 5:19 am
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Is there a better approach to varying the coefficients of a digital IIR over time to adjust the values of its poles and zeros than just recalculating the whole thing every time it changes? For example, lots of synth programs can apply an LFO to the cutoff frequency of a low/high pass filter. I can do some polynomial multiplication to get the coefficients for an IIR filter given its poles and zeros, but am wondering if there is a better way to adjust them over time than simply doing all the calculations over again for new poles/zeros. Particularly, I'm curious if there is a method that will more or less work for an arbitrary number of poles and zeros. You could use a filter implementation (state space) that directly uses the pole/zero values instead of a polynomial. That might be computationally more expensive, though (as you are taking a trip through the domain of complex numbers even though your inputs and output are real), and possibly numerically iffy.As far as I am aware, modifying filter behavior while introducing as few artefacts as possible is still an area of research. You might get away with just adjusting the filter coefficients if you do it slowly, but this does not mean this is the best method.In an audio application, I assume they do not switch filter coefficients abruptly, but instead do a cross-fade between the (settled) first filter and the (mostly or completely settled) target filter to avoid audible artefacts

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Encounter ECO metal mask change

November 13, 2019, 7:41 am
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Hi, 

In the first Encounter ECO run I executed command ( instructing the tool to use metal layers 1-4 ):

ecoDesign -postMask -modifyOnlyLayers 1:4  …. and it seems to work fine.

Latter I was asked to try the  Encounter ECO run using only metal layer 4 so I tried a following command:

ecoDesign -postMask -modifyOnlyLayers 4 .... but I got feedback that ECO change was same as before.

Is it possible to instruct Encounter ECO to run using only one metal layer in metal mask only change of existing digital block layout ?

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Varying a digital IIR filter's poles&zeros over time

November 14, 2019, 6:24 am
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Is there a better approach to varying the coefficients of a digital IIR over time to adjust the values of its poles and zeros than just recalculating the whole thing every time it changes? For example, lots of synth programs can apply an LFO to the cutoff frequency of a low/high pass filter. I can do some polynomial multiplication to get the coefficients for an IIR filter given its poles and zeros, but am wondering if there is a better way to adjust them over time than simply doing all the calculations over again for new poles/zeros. Particularly, I'm curious if there is a method that will more or less work for an arbitrary number of poles and zeros. You could use a filter implementation (state space) that directly uses the pole/zero values instead of a polynomial. That might be computationally more expensive, though (as you are taking a trip through the domain of complex numbers even though your inputs and output are real), and possibly numerically iffy.As far as I am aware, modifying filter behavior while introducing as few artefacts as possible is still an area of research. You might get away with just adjusting the filter coefficients if you do it slowly, but this does not mean this is the best method.In an audio application, I assume they do not switch filter coefficients abruptly, but instead do a cross-fade between the (settled) first filter and the (mostly or completely settled) target filter to avoid audible artefacts.

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Special Route not connecting to Power Rings

November 17, 2019, 5:15 am
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Hi,

I'm a newbie and I'm working on a mixed-signal chip in Innovus. I've got a few analog LEF files that I've imported into my floorplan as macros.

My chip has got two power domains - VCC and VBAT.

One of the macro in the VBAT domain uses VBAT and GND as power rails.

On doing Special-Route, I've got a lot of minute power rails for the standard cells, as expected.

But, the VBAT power rails are not getting extended till the outer power rings. Only the GND rails are correctly getting extended till the outer power rings.

A screen shot is attached for reference.

Thanks for any help

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Stylus flowtool

December 12, 2019, 10:28 am
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Hi,

  I wanted to open a discussion on the stylus flowtool.  My purpose is to see if there are users out there who are having success with the tool.  To have some discussions around issues that I am running into and to get a user point of view on the problems I am trying to solve.

  Let's start the conversation with : Is there anyone out there trying to use flowtool?  Do you have a centralized flow, or each user has their own?

Thanks, and I look forward to the conversations...

--Craig Crump

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About using Liberate to create .lib for a cell with two separate outputs.

December 17, 2019, 6:56 pm
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Hello, my name is Hsukang. I want to use Liberate to create a .lib file for the following circuit. This is a scan FF with two separate outputs.   The question is that no matter how I described its function, the synthesis tool said its a manformed scan FF.  Has anyone ever encountered anything like this？How should I describe the function correctly？I found that almost standard flip-flop cells are with only one output Q or have Qn at the same time. Does Liberate support scan flip-flop cells with two separate outputs ？

Thanks.

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Special Route not connecting to Power Rings

December 31, 2019, 7:47 am
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Hi,

I'm a newbie and I'm working on a mixed-signal chip in Innovus. I've got a few analog LEF files that I've imported into my floorplan as macros.

My chip has got two power domains - VCC and VBAT.

One of the macro in the VBAT domain uses VBAT and GND as power rails.

On doing Special-Route, I've got a lot of minute power rails for the standard cells, as expected.

But, the VBAT power rails are not getting extended till the outer power rings. Only the GND rails are correctly getting extended till the outer power rings.

A screen shot is attached for reference.

Thanks for any help

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What's the difference between Cadence PCB Editor and Cadence Allegro?

January 2, 2020, 1:15 am
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Are they basically the same thing? I am trying to get as much experience with Allegro since a lot of jobs I am looking at right now are asking for Cadence Allegro experience (I wish they asked for Altium experience...). I currently have access to PCB Editor, but I don't want to commit to learning Editor if Allegro is completely different. Also walmart one, are the Cadence Allegro courses worth it? I won't be paying for it and if it's worth it, I figure I might as well use the opportunity to say I know how to use two complex CAD tools.

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Cadence SoC Encounter 8.1 - Keyboard is not working

January 21, 2020, 1:45 pm
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Hello, I am using Encounter 8.1. My mouse is working fine, but my keyboard is not working well in Encounter. I can type in some boxes, but in many boxes I cannot type. The binding key is also not responding. How do I fix this issue? Thanks.

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LVS Error

January 27, 2020, 7:52 pm
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Hi, I am new to cadence. I started out designing an inverter and ran LVS. I made sure that the labels are matching in both schematic and layout. But I run into the following error while LVS  stating that "No matching sub-ckt found for NFET and PFET". Can someone provide insight into this?

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regarding digital flow

February 1, 2020, 3:11 am
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Respected sir,

How can i design and simulate cmos inverter using digital flow and also ineed to do prelayout ans post layout for the same cmos inverter..can i use cadence encounter for this experiments

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Voltus power analysis

February 2, 2020, 6:52 am
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Hi,

I was wondering if it is possible to save the coordinates of each stripe and row of the power grid 

and if it is possible to find out the effective resistance between two given points using Voltus

My goal is to built a resistance model of the power grid

Thanks

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License Issue

February 6, 2020, 9:00 pm
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This are the Errors i am getting can you please provide the solution.

Checking out license: Genus_Synthesis (12 seconds elapsed).
License 'Genus_Synthesis' (main version: 17.2, alternate version: 17.2) checkout failed.
Checking out license: Virtuoso_Digital_Implem (12 seconds elapsed).
License 'Virtuoso_Digital_Implem' (main version: 17.1, alternate version: 17.1) checkout failed.
Checking out license: Virtuoso_Digital_Implem_XL (12 seconds elapsed).
License 'Virtuoso_Digital_Implem_XL' (main version: 17.1, alternate version: 17.1) checkout failed.
Cannot obtain 'Genus_Synthesis' license.
Abnormal exit.

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Innovus Stylus Common UI

February 10, 2020, 9:48 am
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How can I make innovus start with common UI instead of legacy? When I launch Innovus with command "innovus", I get the legacy UI. I have Innovus version 17.11 installed. 

Thanks in advance.

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How do I write the LEF view of a power pad

February 19, 2020, 10:13 am
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I have a set of pads for use in a design and I was wondering which attributes should I put on each pin.

Let's say it has the following pins:

   - inh_vdd, inh_vss, CORE, PAD where the first two are for the pad rings, the CORE pin is to use in the die and the PAD pin is the bonding pad.

I guess CORE would need:

   CLASS CORE

   USE POWER  (or GROUND if this happened to be a ground pad)

What about the inh_vdd and inh_vss? Theyu would not have the CLASS CORE, but would I use USE POWER/GROUND on them too?

   USE POWER (or GROUND)

   SHAPE ABUTMENT

And the bonding pad? Should I put it in the LEF? Or would that cause confusion to innovus or Voltus? And what attributed would it use? USE POWER/GROUND only?

Do I need anything in the LEF to indicate that the pin CORE and the pin PAD are essentially the same thing, just different places on the same power pad?

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