I have been using Voltus to do IR drop analysis but I got caught on one signal. It is negative. When I use:
set_pg_nets -net negsupply -voltage -5 -threshold -4.5 -package_net_name NEGSUP -force
Voltus dies with a backtrace. Looking at the beginning of the trace you see it suggests that the problem is it set maximum to -5 and minimum to 0. Is there another way to express a negative voltage supply for IR drop analysis?
I recently received a student version or OrCad, which I was able to download and install without trouble. However, I do not know how to setup my license.
I received the license file in an email. The instructions within the file were to include my hostname and the absolute path. I do not know what the path should point to so I left it empty.
I was able to setup the licence server using the license file without any issues. However, setting up the licence configuration utility gives the following messages:
A user environment variable name CDC_LIC_FILE is found. The CDC_LIC_FILE settings you make will be overwritten by this user level variable. Furthermore, I get the error:
ERROR: Unable to update the CDS_LIC_FILE license path environment variable.
This is preventing me from using any of the software.
What are the steps to installing the license and how could I resolve this error?
Thank you
Hello everyone,
I am Vinay and I am currently developing some digital circuits for my chip design for my master's thesis at University at Buffalo.
I am fairly very new to Verilog and I don't seem to follow some of the things others find very easy.
Following are the things that I want to do to which I have no clue:
1. Develop certain arithmetic functionality in Verilog
2. Generate netlist for the verilog code
3. Feed the netlist file to Cadence encounter to be able to generate Digital Circuits' layout for my chip
I can use Cadence Virtuoso and Encounter for this but I don't know the exact procedure to get this done.
Could someone please describe the detailed process for doing the things mentioned above.
Thank you.
According to the book Electronic Design Automation For Integrated Circuits Handbook there are mutiple algorithms available. Quote from book: "One of the first complete ATPG algorithms is the D-algorithm [9]. Subsequently, other algorithms were proposed, including PODEM [14], FAN [15], and SOCRATES [10]."
I was wondering which algorithms are used in Cadence Modus.
Hi!
In my design, there is an one hold violation on scan path, test data is corrupted during scan cycles (when i run verilog simulation of test vectors). I created constraint 'falsepath' to 'TI' input of violated flop and load it into Modus, but this does not have effect.
Can enyone explain to me, does 'falsepath' constraint affects scan path (from Q to TI/SI input, i.e. during SCAN procedure) or this constraint is only for functional mode (ie affects TEST cycle only - to 'D' input)?
I hope resolve this problem this by using some modus design constraints or any other method.
hope someone could shed light on it.
the log file is here
https://gitee.com/chaujohnthan/temporal/blob/master/VDIVceToInn.logv
I found some glitch filter design on the internet but I am unsure of how to set a typical value for the the glitch delay.
Assume the clock speed is 800MHz on a die of 3*3mm at 28nm. How should one decide for that delay?
Thank you in advance.
I have completed physical design of a block in innovus. I want to extract rc of that block using quantus . It will be very helpful if you give step by step procedure and command to run quantus to extract rc of that block.
Hi,
When I import the top level Verilog file generated by Genus into Virtuoso, the power pins are left unconnected. I tried different configurations in "Global Net Options" tab. However, nothing changed.
The cell is imported with three views, namely functional, schematic, and symbol. In www krogerfeedback com functional view everything looks OK, that is the top level Verilog file. In schematic, I can see the digital cells but VDD and VSS pins of the blocks are not connected. In the symbol view there are no pins for VDD and VSS.
On top, we are trying to implement a digital block into Virtuoso. The technology is TSMC 65nm. On Genus and Innovus, everything goes straight and layout is generated successfully.
Thanks.
Hello,
I created a floorplan view in Virtuoso ( it contains pins and blockages). I am trying to run PnR in Innovus for floorplan created in Virtuoso. I used set vars(oa_fp) "Library_name cell_name view_name" to read view from virtuoso. I am able to see pins in Innovus but not the blockages. Can i know how do i get the blockages created in virtuoso to Innovus.
Regards,
Amuu
HI, I have been using the Innovus GUI commands for several things and wonder if those command can be written to a log or cmd file so I can use it in my flow script? Is there such options that we can set?
Thanks
Hi,
I am doing layout for a mixed-signal circuit in Innovus. I want to create a digital donut style of layout (i.e. put analog circuit in the middle, and circle analog part with digital circuits).
To do that, I need to place some pins inside the edge to connect to analog circuit (as shown in my attachment), but the problems is that I cannot place pins inside the edge by using "pin editor" within Innovus. Any suggestions to place pins inside?
Thank you so much for your time and effort.
Hello Everyone,
I was finishing the layout via Innovus and ran verifyConnectivity followed by checkRoute.
verifyConnectivity was okay and it showed no errors and no warnings, whereas checkRoute showed there are 3 unrouted nets.
When i ran the checkRoute command again immediately, it showed no unrouted/unconnected nets.
Which of these commands should we trust or is this really unrouted nets issue?
Looking forward for a response, thanks in advance.
Regards,
Vijay
Hi,
There was tool available with INCISIV called imc to view the coverage reports.
The question is: How can we view the code coverage reports generated with XCELIUM? I think imc is not available with XCELIUM?
Thanks in advance.
Hi,
Given the power consumption of a design, how can we go about designing the power grid for the design in Innovus? Is there a method to compute the minimum width for the rings and stripes, via nos, decap, etc?
Which all tools can be used for this?
Thanks and Regards
Varun M J
Hi,
Given the power consumption of a design, how can we go about designing the power grid for the design in Innovus? Is there a method to compute the minimum width for the rings and stripes, via nos, decap, etc?
Which all tools can be used for this?
Thanks and Regards
Varun M J
One way is to exit the tool. I tried a few things but couldn't find such basic command.
Hello IC Designs.
I want some information about the DLI (Defect Location Identification) algorithm based in Modus IC Test.
I have some difficults to understand the branching for DLI.
also some fundamental concepts like:
Any information are very grateful.
Evandson.
A reference paper for my question: http://www.es.ele.tue.nl/~kgoossens/2019-lats.pdf
Hi,
I am getting 47 Process Antenna Violations after routing my design, all these violations are on intermediate layers. When I try to run Nanoroute(modes mentioned below), it does not adds any antenna diode to fix the violations, please suggest how to clean these violations using Nanoroute.
-dbAdjustAutoViaWeight true # bool, default=true
-dbAllowInstanceOverlaps false # bool, default=false
-dbIgnoreFollowPinShape false # bool, default=false
-dbProcessNode {} # string, default=""
-dbRcExtractionCorner {} # string, default=""
-dbSkipAnalog false # bool, default=false
-dbViaWeight {} # string, default=""
-drouteAntennaEcoListFile {} # string, default=""
-drouteAutoStop true # bool, default=true
-drouteEndIteration 0 # int, default=0
-drouteFixAntenna true # bool, default=true, user setting
-drouteFixViaDensityViolationAfterViaSwap false
# bool, default=false
-drouteMaskOnlyOnLayer false # string, default=false
-drouteMinLengthForWireSpreading 0 # string, default=0
-drouteMinLengthForWireWidening 1 # float, default=1
-drouteMinSlackForWireOptimization 0 # float, default=0
-drouteNoTaperInLayers {} # string, default=""
-drouteNoTaperOnOutputPin false # ternary, default=false
-drouteOnGridOnly none # string, default=none
-droutePostRouteLithoRepair false # bool, default=false
-droutePostRouteSpreadWire 1 # string, default=auto, user setting
-droutePostRouteSwapVia false # string, default=false
-droutePostRouteSwapViaPriority auto # string, default=auto
-droutePostRouteWidenWire none # string, default=none
-droutePostRouteWidenWireRule {} # string, default=""
-drouteSearchAndRepair true # bool, default=true
-drouteSignOffEffort high # string, default=high
-drouteStartIteration 0 # int, default=0, user setting, obsoleteWarn
-drouteUseMultiCutViaEffort low # string, default=low
-envNumberFailLimit 0 # int, default=0
-envNumberProcessor 1 # int, default=1
-envNumberWarningLimit 0 # int, default=0
-envThirdPartyData false # bool, default=false
-hfrouteConstraintFile {} # string, default=""
-hfrouteConstraintGroups {} # string, default=""
-hfrouteMatchReportFile {} # string, default=""
-hfrouteNumReserveLayers 1 # int, default=1
-hfrouteRemoveFloatingShield false # bool, default=false
-hfrouteSearchRepair false # string, default=false
-hfrouteShieldTrimLength 0 # float, default=0
-routeAllowPinAsFeedthrough true # string, default=true
-routeAntennaCellName ANTENNA_T3_12T_DG24RVT
# string, default="", user setting
-routeAntennaPinLimit 1000 # int, default=1000
-routeBottomRoutingLayer 0 # int, default=0
-routeConcurrentMinimizeViaCountEffort medium
# string, default=medium
-routeConnectToBump false # bool, default=false
-routeDesignFixClockNets false # bool, default=false
-routeDesignRouteClockNetsFirst true # bool, default=true
-routeEnableNdrSiLimitLength false # string, default=false
-routeEnforceNdrOnSpecialNetWire false # string, default=false
-routeExtraViaEnclosure 0 # float, default=0
-routeFixTopLayerAntenna true # bool, default=true
-routeHonorPowerDomain false # bool, default=false
-routeIgnoreAntennaTopCellPin true # bool, default=true
-routeInsertAntennaDiode true # bool, default=false, user setting
-routeInsertDiodeForClockNets false # bool, default=false
-routeRelaxedNdrSpacingToPGNets none # string, default=none
-routeReserveSpaceForMultiCut false # bool, default=false
-routeReverseDirection {} # string, default=""
-routeSelectedNetOnly false # bool, default=false
-routeShieldCrosstieOffset {} # string, default=""
-routeStrictlyHonorNonDefaultRule false # string, default=false
-routeStripeLayerRange {} # string, default=""
-routeTieNetToShape auto # string, default=auto
-routeTopRoutingLayer 0 # int, default=0
-routeTrimPullBackDistanceFromBoundary {}
# string, default=""
-routeTrunkWithClusterTargetSize 1 # int, default=1
-routeUnconnectedPorts false # bool, default=false
-routeWithEco true # bool, default=false, user setting
-routeWithLithoDriven false # bool, default=false
-routeWithSiDriven false # bool, default=false, user setting
-routeWithSiPostRouteFix false # bool, default=false, user setting, private
-routeWithTimingDriven false # bool, default=false, user setting
-routeWithViaInPin false # string, default=false
-routeWithViaInPinSingleMask false # bool, default=false
-routeWithViaOnlyForMacroCellPin false # string, default=false
-routeWithViaOnlyForStandardCellPin false
# string, default=false
-timingEngine CTE # string, default=CTE, user setting, private
Thanks
Utkarsh
Hi,
I am trying to place and rout a simple test design using Innovus foundation flow.
But at the end of the flow, I get a short between nets and cell blockage.
I tried to increase the designed area to a huge value (1mm x 1mm) but the short remains.
The design density is at 43%.
You can see en example of short in this picture. The short is on M1.
Thank you in advance for your time.
