Cannot apply preserve attribute in VHDL source file

August 11, 2020, 2:14 pm

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Hello,

we are currently synthesizing a design that contains some triple modular redundancy and we want to keep Genus from throwing out whats redundant. So we tried to set the "preserve" attribute in our VHDL file. Putting it on instances gave us errors because it could not be applied to unmapped instances. Applying it to the signals in question did not change anything.

Then my collegue put the "preserve" attribute on the exact same signals through the "set_dont_touch" command in Genus and it worked perfectly fine.

So I am a bit confused now. Is it just impossible to set attributes in the VHDL source file or am I doing something wrong? I also checked that the attributes are read in my FPGA tool which I use to test the code. Of course it does nothing with that attributes, it uses its own, but it still reads and displays them. So the syntax seems correct.

Thank you in advance for any help

Genus Version is 17.22

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**WARN: (IMPESI-429): No RC available on net xxx in INNOVUS 19.13

August 21, 2020, 2:48 am

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Hi,

during optDesign postRoute log show a lot of warning IMPESI-429, what could be the reasons? 

set_multicycle_path questions

September 3, 2020, 7:29 pm

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1. For multicycle path constraint , what is the difference between the usage of -start and -end ?

2. Why "hold will return back to 0 cycle check" ?

3. How to derive the hold_cycles equation ?

Genus - Hierarchy

September 4, 2020, 2:44 am

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Hi,

I am building my circuit which involves a top level and several sub-modules.

I am interested in details about these sub-modules, but after the synthesis (syn_generic), the hierarchy is lost and I can't access these sub-modules any more.

Any ideas?

Thanks

Reporting non-RC gated flops

September 9, 2020, 5:21 am

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The report_clock_gating command prints out a summary of the number of RC-gated flops, non-RC-gated flops, and ungated flops. Using the -gated_ff or -ungated_ff options the commands prints details about the gated or ungated flops.

Is there a way to get details about the non-RC gated flops without getting the details about all gated flops? Typically this report becomes very long if all gated flops in a design are listed (as with the -gated_ff option).

How to highlight data path between given start point and end point

September 14, 2020, 4:24 am

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I want to highlight a data path from a given pin of an instance to a given pin of an instance is there any way to do it?

Dsp hifi 4 FFT output scaling issue

September 25, 2020, 6:25 am

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hi,

  i am doing RFFT with N=32 on RT1060 board and RT600 board. but when i match the FFT output with online fft data.

 the RT600 FFT output not matching. RT1060 output is matching.

  Can you please clear me how can i interpret the output with differrent scaling .

Also there are two functions for FFT , i have used "fft_real32x32" 

but i want to use "fft_realf_ie" but dont know how to get "twiddle factor table of a complex-valued
FFT of size N*twdstep" and twstep.

can you please help me out...

Problem in reporting set_data_check in Genus 19

September 29, 2020, 3:58 am

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Hello,

I am experiencing some issues in reporting the outcome of the SDC constraint set_data_check. Briefly, I am trying to constraint the delay between two input pins of a combinational gate, with the classic -from -to syntax. Genus is able to recognize correctly the constraint in the SDC but I cannot get anything useful from the report_timing command, neither specifying directly the path. As specified in the user guide, I am also setting enable_data_check to true before importing the design and timing_disable_non_sequential_checks is set to false.

Do you have any suggestion?

dbellix

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What is the Syllabus for CADENCE Exam?

October 7, 2020, 11:06 am

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I Want To Know The Required Syllabus For The CADENCE Placement Test.

Timing effect when using setNanoRouteMode -drouteEndIteration in Innovus

October 10, 2020, 7:32 pm

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Hi all,

I'm using Innovus for PnR and in route step, i don't want the tool to fix physical DRC violations ( not tran/cap/fanout) during route optimiztion and i'm using this option:

setNanoRouteMode -drouteEndIteration 1

In my understanding, the tool will fix DRC in 1 iteration in detail routing and optimization step. I see it works well but i'm wondering if this option affect to timing optimization iteration or not? Or it only affects to DRC.

Could anyone help to give me some comments?

Or if someone has another way to reduce/disable DRC fixing, could you let me know?

Thanks.

Extracting LEF Hierarchically in Innovus

June 8, 2020, 8:38 am

≫ Next: route plus shield selected net

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Hello,

I am currently using Innovus to build a hierarchical design where the levels of hierarchy can range from 2 to 6/7. I'm having some issues right now getting the -extractBlockObs flag to work for the write_lef_abstract command. It does not seem to want to pull the obstruction information from my lower level LEF(s). I verified that they are marked as CLASS BLOCK. Any suggestions?

Also, on a side note, is there any way for write_lef_abstract to extract VIA information? This would be extremely useful in my current flow, but I have been unable to get this to work as of now.

route plus shield selected net

October 12, 2020, 10:50 am

≫ Next: check point to point resistance for power and and analog nets

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HI,

I want to know is there any way In which I can pre-route some nets with shielding, Shielding should be on only selected nets not others.

Please let me know if anyone knows about it.

Thanks

Japesh

check point to point resistance for power and and analog nets

October 12, 2020, 10:52 am

≫ Next: Sroute not connecting pads

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HI,

I want to know is there any way In which I can check point to point resistance for analog/power nets

Please let me know if anyone knows about it.

Thanks

Japesh

Sroute not connecting pads

October 13, 2020, 3:49 am

≫ Next: power nets not connected to PAD M3

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Hello,

I am using command      sroute -connect { padPin padRing } -layerChangeRange { M1(1) LB(9) } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -padPinTarget { nearestTarget } -corePinCheckStdcellGeoms -allowJogging 1 -crossoverViaLayerRange { M1(1) LB(9) } -area { 1076.874 1428.067 1190.36 1216.186 } -nets { VDD_CORE GNDS_CORE } -allowLayerChange 1 -targetViaLayerRange { M1(1) LB(9) }

 However , The VDD_CORE and GNDS_CORE nets are not connected to respective pads.

I also get warning:

**WARN: (IMPSR-1254): Cannot find any block pin of net VDD_CORE. Check netlist, or change option to include the pin.

VDD_CORE is definately in the netlist

power nets not connected to PAD M3

October 16, 2020, 12:18 am

≫ Next: VHDL IEEE Library not recognized by RTL Compiler or Genus

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Hello,

I am using sroute command

sroute -connect { blockPin padPin padRing corePin floatingStripe } -layerChangeRange { M1(1) LB(9) } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -padPinTarget { nearestTarget } -deleteExistingRoutes -allowJogging 1 -crossoverViaLayerRange { M1(1) LB(9) } -area { 1076.874 1428.067 1190.36 1216.186 } -nets { VDD_CORE GNDS_CORE } -allowLayerChange 1 -targetViaLayerRange { M1(1) LB(9) } 

To connect Power and ground nets VDD_CORE and GNDS_CORE to respective PADs

The PG pins in pads are in M3 layer ( metal 3)  .

When looking at the innovus GUI  I can not see the M3  layer in PADS and looks that the the nets are NOT connected.

How can I get them connected?

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VHDL IEEE Library not recognized by RTL Compiler or Genus

October 20, 2020, 7:30 pm

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Hello,

I guess this is a dumb question but I didn't find any having the same issue as mine or any tutorial to guide me through this process...

I wanted to synthesize a design written in VHDL with either RC or Genus, but I got the same error (and the error repeats for each VHDL file...)

library IEEE;
        |
Error : Missing token. [VHDLPT-672] [read_hdl]
: library clause requires ';', read <identifier> IEEE in file 'addroundkey.vhd' on line 46, column 9.

I guess I need to explicitly point to the IEEE library, which I am not sure how to do. Any insight would be greatly appreciated!

Yuntao

InnoVus Sroute IMPSR-2405

October 22, 2020, 12:50 am

≫ Next: Innovus Stylus Common UI Global Net Connection

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Hi,

I am running sroute in Innovus ang get warning : (IMPSR-2405): Specified pin WIRECELL_EXT_CSF_FC_LIN ANAIO does not match db pin.

The power and ground nets are not correctly connected to pads, so I suspect this warning has something to do with it. How to correct this?

I am using INNOVUS v19.11

Also I have found a error report on this Innovus version: CCMPR02290918 sroute fails to connect some stripes to pad pins

Is there a workaround to this ?

Could this actually be the root cause to the warning?

BR. Sirpa

Innovus Stylus Common UI Global Net Connection

November 16, 2020, 3:19 pm

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Hi everyone.

I'm new to Innovus and I would like to know if it is possible to use the Global Net Connection option, that is present in the Power tab, also in the Stylus Common UI option.

I know that it can be done by code using che command connect_global_net but I would like to know if this option is present also in the GUI of the Stylus mode.

Thank you

Label oa_purpose

November 20, 2020, 1:21 pm

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Hi,

The labels I am creating in Innovus have the Purpose of "drawing" by default. This is causing me issues in OA. When I try to change the Purpose from "drawing" to "pin" using -oa_purpose {pin}, I get the following error:

"**ERROR: (IMPDBTCL-4005): The specified -oa_purpose name ('pin') is not a purpose name for OA purpose from the technology graph or the design is an OA based design".

How can I resolve this error in Innovus? Do I need to initialize purpose names? Thank you.

Auto-routing

December 4, 2020, 5:27 am

≫ Next: trouble with auto routing minimum spanning tree, Layout XL

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Hello,

I'm having trouble with virtuoso 6.1.7 layout XL auto-routing.

To show you my problem i created a hierarchical design consisting of two inverters in the first hierarchy, and a third inverter in the last hierarchy.  The structure should be visible in the image below: the big red square is the lower hierarchy, meanwhile on the top right i have the third inverter belonging to the higher hierarchy.

I would like the minimum spanning tree to wire the input of the third inverter to any positions of the blue line that connect the 2 inverters of the first hierarchy.

Since I am using the minimum spanning tree, I would expect the gray line to be the shortest, but instead the auto-routing is routing it to the pin i placed around the middle point of the horizontal blue line(that little blue square): in fact if I move the pin around the gray line follows it. I've tried using the layer generation tool to automatically cover the blue line with the blue metal pin, but the problem still occurs: the auto-route wire the net to that specific pin. I think that is because the auto-route consider that little blue square (the pin generated from the schematic) the terminal of the net.

How can i tell the auto-route that it can connect to any points of the blue line, and not just where i placed the pin generated from the schematic?

Right now the only solution i have to this problem is to flatten the layout, but i would prefer to avoid this solution and keep a hierarchical design.

Thanks

Best regards, Andrea