Hi.

I want to synthesize a digital block prioritizing a custom Verilog netlist made of standard cells. I have created the following module as AOI.v file:

I encounter the following command while reading the SDC:

• create_generate_clock [list [get_pins pciex4_2_clk] [get_pins pciex4_2_clk_clks]] -name pciex4_2 -source [get_port xx ] -dvide_by 1

Now I know this constraint can be enforced, but I wonder when such a constraint is necessary?

By the way, I'd like to consult the difference between [get_ports] and [get_pins] when create_generated_clock?

Thanks a lot if anyone could anwser my questions.

Hi, when I try to load in design to Innovus, it returns error message:

Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
**ERROR: (IMPVL-209): In Verilog file '../RTL_codes/models_pack.v', check line 7 near the text @ for the issue: 'syntax error'. Update the text accordingly.
Type 'man IMPVL-209' for more detail.
Verilog file '../RTL_codes/models_pack.v' has errors! See above.

*** Memory Usage v#1 (Current mem = 908.020M, initial mem = 290.477M) ***
#% End Load netlist data ... (date=12/13 00:08:57, total cpu=0:00:00.0, real=0:00:00.0, peak res=861.0M, current mem=861.0M)
**ERROR: (IMPVL-902): Failed to read netlist ../RTL_codes/N_term_single_switch_matrix.v ../RTL_codes/models_pack.v ../RTL_codes/N_term_single_tile.v. See previous error messages for details. Resolve the issues and reload the design.
innovus 1>

When I type 'man IMPVL-209', it returns : 

IMPVL-209(20.15) IMPVL-209(20.15)

NAME
IMPVL-209

SUMMARY
In Verilog file '%s', check line %d near the text %s for the issue:
'%s'. Update the text accordingly.

DESCRIPTION
This message reports the location of the text causing a warning or
error situation in the input netlist file, which is briefly described
by the last argument text. Update the source text accordingly to
resolve the issue.

IMPVL-209(20.15)

And my code is : 

module LHQD1 (input D, E, output reg Q, QN);
always @(*)
begin
if (E == 1'b1) begin
Q = D;
QN = ~D;
end
end
endmodule

What error message mentioned is 'always @(*)', I cannot find where the syntax error is, can you help me?

Hi everyone, 

In our design we will be performing a top-level PnR in Innovus, where we will be routing between blocks (macros) as well as routing the pads to the blocks. 

I was wondering if there was any way to create a region and confine the power routing from a pad to a block? For example, let's say routing power from a 1.2V pad to a PLL. I know there is a function in Innovus called "Bus Guide," where you can confine the signal routing between blocks within a region you create, after defining a particular net group. However, I am not sure if that would work for routing between a pad and a block, let alone routing power. 

I would appreciate any insight. 

Thank you, 

Suzanne 

I'm using Innovus 18.10 and there is some error with placement and I could not find out why. The server CPU has 112 cores. Innovus used 64 threads, which was set by "set_multi_cpu_usage -local_cpu 64". The stack size was maximum, set by bash command "ulimit -s unlimited". I once tried running the same tcl script and same design with 16 threads and Innovus completed everything normally.

Here's part of the log file:

@file(par.tcl) 277: place_opt_design
No user sequential activity specified, applying default sequential activity of "0.2" for Dynamic Power reporting.
'set_default_switching_activity' finished successfully.
*** Starting GigaPlace ***
**INFO: user set placement options
root: { place_detail_check_cut_spacing {true} place_global_activity_power_driven {false} place_global_activity_power_driven_effort {standard} place_global_clock_power_driven {true} place_global_clock_power_driven_effort {standard} place_global_cong_effort {high} place_global_place_io_pins {true} place_global_uniform_density {true}}
**INFO: user set opt options
root: { opt_all_end_points {true} opt_area_recovery {true} opt_consider_routing_congestion {auto} opt_fix_fanout_load {true} opt_fix_hold_allow_overlap {auto} opt_honor_density_screen {true} opt_leakage_to_dynamic_ratio {0.2} opt_post_route_area_reclaim {none} opt_post_route_drv_recovery {auto} opt_post_route_setup_recovery {true} opt_power_effort {low}}
#optDebug: fT-E <X 2 3 1 0>
**Info: (IMPSP-307): Design contains fractional 20 cells.
*** Start delete_buffer_trees ***
Multithreaded Timing Analysis is initialized with 64 threads

Info: Detect buffers to remove automatically.
Analyzing netlist ...
Updating netlist
AAE DB initialization (MEM=3170 CPU=0:00:00.2 REAL=0:00:00.0)

*summary: 14621 instances (buffers/inverters) removed
*** Finish delete_buffer_trees (0:00:29.3) ***
**INFO: No dynamic/leakage power view specified, setting up the setup view "PVT_0P63V_100C.setup_view" as power view
** WARN: (VOLTUS_POWR-3212): The 'set_power_analysis_mode -leakage_power_view |-dynamic_power_view|-analysis_view' will be obsolete in 18.20 release. Use 'set_analysis_view -leakage <> | -dynamic <>' to set leakage and dynamic power views.

PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view

Power Net Detected:
Voltage Name
0.00V VSS
0.63V VDD
#################################################################################
# Design Stage: PreRoute
# Design Name: ChipTop
# Design Mode: 7nm
# Analysis Mode: MMMC OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
PVT_0P63V_100C.setup_view PVT_0P77V_0C.hold_view
0.00V VSS
0.63V VDD
clock_clock(500MHz) CK: assigning clock clock_clock to net axi4_mem_0_clock

Starting Levelizing
2023-Jan-10 22:56:18 (2023-Jan-11 04:56:18 GMT)
2023-Jan-10 22:56:19 (2023-Jan-11 04:56:19 GMT): 10%
2023-Jan-10 22:56:19 (2023-Jan-11 04:56:19 GMT): 20%
2023-Jan-10 22:56:19 (2023-Jan-11 04:56:19 GMT): 30%
2023-Jan-10 22:56:20 (2023-Jan-11 04:56:20 GMT): 40%
2023-Jan-10 22:56:20 (2023-Jan-11 04:56:20 GMT): 50%
2023-Jan-10 22:56:21 (2023-Jan-11 04:56:21 GMT): 60%
2023-Jan-10 22:56:21 (2023-Jan-11 04:56:21 GMT): 70%
2023-Jan-10 22:56:22 (2023-Jan-11 04:56:22 GMT): 80%
2023-Jan-10 22:56:22 (2023-Jan-11 04:56:22 GMT): 90%

Finished Levelizing
2023-Jan-10 22:56:23 (2023-Jan-11 04:56:23 GMT)

Starting Activity Propagation
2023-Jan-10 22:56:23 (2023-Jan-11 04:56:23 GMT)
** INFO: (VOLTUS_POWR-1356): No default input activity has been set. Defaulting to 0.2.
Use 'set_default_switching_activity -input_activity' command to change the default activity value.

2023-Jan-10 22:56:31 (2023-Jan-11 04:56:31 GMT): 10%
2023-Jan-10 22:56:34 (2023-Jan-11 04:56:34 GMT): 20%

Finished Activity Propagation
2023-Jan-10 22:56:43 (2023-Jan-11 04:56:43 GMT)
**Info: max transition density of cached activity is: 1e+09

Deleted 0 physical inst (cell - / prefix -).
Did not delete 207651 physical insts as they were marked preplaced.
INFO: #ExclusiveGroups=0
INFO: There are no Exclusive Groups.
Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
Extracting macro/IO cell pins and blockage ......
Pin and blockage extraction finished
No user-set net weight.
Net fanout histogram:
2 : 379071 (63.9%) nets
3 : 89194 (15.0%) nets
4 - 14 : 110401 (18.6%) nets
15 - 39 : 9614 (1.6%) nets
40 - 79 : 3624 (0.6%) nets
80 - 159 : 724 (0.1%) nets
160 - 319 : 115 (0.0%) nets
320 - 639 : 49 (0.0%) nets
640 - 1279 : 1 (0.0%) nets
1280 - 2559 : 0 (0.0%) nets
2560 - 5119 : 0 (0.0%) nets
5120+ : 2 (0.0%) nets
**WARN: (IMPSP-196): User sets both -place_global_uniform_density and -place_global_initial_padding_level options. Overriding -place_global_initial_padding_level to 5.
Options: timingDriven clkGateAware ignoreScan pinGuide congEffort=high gpeffort=medium
Scan chains were not defined.
#std cell=855381 (207651 fixed + 647730 movable) #buf cell=0 #inv cell=64869 #block=535 (0 floating + 535 preplaced)
#ioInst=0 #net=592795 #term=2233984 #term/net=3.77, #fixedIo=0, #floatIo=0, #fixedPin=362, #floatPin=0
stdCell: 855381 single + 0 double + 0 multi
Total standard cell length = 1237.7966 (mm), area = 1.3368 (mm^2)
**Info: (IMPSP-307): Design contains fractional 20 cells.
Average module density = 0.136.
Density for the design = 0.136.
= stdcell_area 5315238 sites (1239939 um^2) / alloc_area 39223032 sites (9149949 um^2).
Pin Density = 0.03756.
= total # of pins 2233984 / total area 59472204.
Identified 64502 spare or floating instances, with no clusters.

Enabling multi-CPU acceleration with 16 CPU(s) for placement
=== lastAutoLevel = 12
Clock gating cells determined by native netlist tracing.
Iteration 1: Total net bbox = 1.760e+07 (1.01e+07 7.51e+06)
Est. stn bbox = 1.959e+07 (1.12e+07 8.39e+06)
cpu = 0:03:37 real = 0:03:37 mem = 4867.4M
Iteration 2: Total net bbox = 1.760e+07 (1.01e+07 7.51e+06)
Est. stn bbox = 1.959e+07 (1.12e+07 8.39e+06)
cpu = 0:00:00.8 real = 0:00:01.0 mem = 4885.2M
*** Finished SKP initialization (cpu=0:03:09, real=0:01:37)***
Iteration 3: Total net bbox = 1.254e+07 (7.39e+06 5.16e+06)
Est. stn bbox = 1.516e+07 (8.79e+06 6.37e+06)
cpu = 0:53:05 real = 0:07:00 mem = 8665.0M
Iteration 4: Total net bbox = 1.946e+07 (1.18e+07 7.63e+06)
Est. stn bbox = 2.445e+07 (1.48e+07 9.62e+06)
cpu = 1:38:56 real = 0:10:09 mem = 10053.8M
Iteration 5: Total net bbox = 1.946e+07 (1.18e+07 7.63e+06)
Est. stn bbox = 2.445e+07 (1.48e+07 9.62e+06)
cpu = 0:00:00.1 real = 0:00:00.0 mem = 10053.8M
Iteration 6: Total net bbox = 2.297e+07 (1.24e+07 1.05e+07)
Est. stn bbox = 3.073e+07 (1.62e+07 1.46e+07)
cpu = 0:49:39 real = 0:04:57 mem = 8770.5M

Iteration 7: Total net bbox = 2.321e+07 (1.27e+07 1.05e+07)
Est. stn bbox = 3.100e+07 (1.64e+07 1.46e+07)
cpu = 0:00:00.8 real = 0:00:01.0 mem = 8537.6M
Iteration 8: Total net bbox = 2.321e+07 (1.27e+07 1.05e+07)
Est. stn bbox = 3.100e+07 (1.64e+07 1.46e+07)
cpu = 0:00:01.1 real = 0:00:01.0 mem = 8537.6M
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/innovus/bin/64bit/innovus[0x10cee9bb]
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/innovus/bin/64bit/innovus(syStackTrace+0x5a)[0x10ceedb1]
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/innovus/bin/64bit/innovus[0x456ae95]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x14420)[0x14e0a2865420]
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/innovus/bin/64bit/innovus(_ZN8spTiming15DelayCalculator16CellArcDelayIter23calcDelayForLinearModelERKNS0_20CellArcDataPerCornerEd+0x9)[0xa0e4149]
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/innovus/bin/64bit/innovus(_ZN8spTiming15DelayCalculator16CellArcDelayIter4nextEv+0x608)[0xa0f56d8]
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/innovus/bin/64bit/innovus(_ZN8spTiming18DelayUpdateServiceIdE14processCellArcEj+0x4e)[0x9fbc7ee]
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/innovus/bin/64bit/innovus[0x9fdb97b]
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/innovus/bin/64bit/innovus(_ZN8spThread12spThreadPool6WorkerIvE4loopEv+0xc7)[0x99aea97]
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/lib/64bit/libnffr.so(execute_native_thread_routine+0x20)[0x14e0a8016b60]
/usr/cadence/INNOVUS/INNOVUS1817/tools.lnx86/innovus/bin/64bit/innovus[0x4814af9]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x8609)[0x14e0a2859609]
/lib/x86_64-linux-gnu/libc.so.6(clone+0x43)[0x14e0a212e133]
========================================
gdb
========================================
Using: gdb
*** Stack trace:

I google searched the tracing "libc.so.6(clone+0x43)" and "libpthread.so.0(+0x8609)". It looks like to be some problem with memory management. 

Is there a way to solve this? What else should I do to let Innovus make use of 64 or even more local threads?

Hi, I have a TCL script for synthesizing a full adder (see below).

I am trying to modify the script so that when Genus opens, the schematic represents the circuit in module form.

I don't want to see the standard cell circuits and would like to see something simple. It seems I have gotten this to happen but I am not sure how.

When I source the script below, Genus opens and I get the first schematic (schematics are shown below). Without closing Genus, I source the script again and get the second schematic (preferred one).

What is happening that is causing the schematic to change when I source the script for a second time? How I can set the script such that the second schematic is by default? Thanks!

#### Include TCL utility scripts..
include load_etc.tcl
#### Set up
set DESIGN fulladder
set SYN_EFF medium
set MAP_EFF medium
set DATE [exec date +%m%d.%H%M]
set map_fancy_names 1
set iopt_stats 1

set SYN_PATH "."
set_db lib_search_path /home/transistor
set_db init_hdl_search_path .
set_db information_level 7
set_db library {transistor.lib}
set_db hdl_array_naming_style %s\[%d\]

set_db tns_opto true

read_hdl ./inputs/dig.v

elaborate $DESIGN

puts "Runtime & Memory after 'read_hdl'"
timestat Elaboration

check_design -unresolved

report timing -lint -verbose

#### Synthesizing to generic
set_db syn_generic_effort $SYN_EFF
puts "Runtime & Memory after 'synthesize -to_generic'"
timestat GENERIC
set_db auto_ungroup none
syn_generic

#### Synthesizing to gates
set_db syn_map_effort $MAP_EFF
puts "Runtime & Memory after 'synthesize -to_map -no_incr'"
timestat MAPPED

syn_map

remove_assigns_without_optimization
set_db syn_map_effort $MAP_EFF
insert_tiehilo_cells
puts "Runtime & Memory after incremental synthesis"
timestat INCREMENTAL

syn_opt

report area > ./outputs/${DESIGN}_area.rpt
report gates > ./outputs/${DESIGN}_gates.rpt
write_hdl > ./outputs/${DESIGN}.vg
write_sdc > ./outputs/${DESIGN}.sdc

gui_show;

1st Schematic 

2nd schematic (preferred)

I wanted to do an IR drop analysis and followed the procedure provided in the Cadence tutorial video: power analysis, specify power net, power pad location file, run rail analysis.

It did not run successfully with the following error:

" ** ERROR: (VOLTUS_RAIL_SMG-0047): Net VDD doesn't have any valid current source (tap) connected, therefore analysis cannot continue. If this is intended to be an incomplete net, please add 'set_rail_analysis_mode -ignore_incomplete_net true' and rerun.
*** Error: Failed to run voltus_rail_smg, return code is 1
*** Error: In processing command script
Power grid merging failed."

The power pad location file looks like this:

" *vsrc_name x y layer_name
  VDDvsrc1 52.665 883.880 G2
  VDDvsrc2 52.665 468.880 G2
  VDDvsrc3 52.665 553.880 G2
  VDDvsrc4 52.665 638.880 G2

..."

Can you provide some advice on how to resolve this ?

Dear all, 

I am trying to run Innovus (v21.11 64bit) on Red Hat 7.9 Linux, the tool tries to run but ultimately a "segmentation fault (core dumped)" message appears. I get the same issue when trying to run it on another machine (with the same tool version and operating system).  I read about this error and it is related to memory access. Could you please provide any information to resolve this issue? 

Kind Regards, 

Qassam 

I have a folder named "seed.enc.dat" file, and my gate level netlist is called "design.v", and its top module is called "SEED_key_sched".

But after I use "ecoDesign ./db/seed.enc.dat SEED_key_sched ./design.v" command, it ran out the error that "Failed to find design data with specified top cell name" . How can I deal with it?

Thank you very much !

I got 5 DRC violations after routing in innovus version 21.13, is there any solution that can solve all these DRC Violations?

Thanks!

Hi all,

After running STA multi-mode-multi-corners I get more than 20 sdf files. I would like to somehow check all of them without running manually more than 20 times xcelium.

Is there any way of doing this? I was thinking of writing a script that generates different argument files for xcelium. each one of them with a different conditional compilation for the testbench, something like this:

Any other ideas? It is a very basic systemverilog testbench, I just want to check timing violations in the log files.

Thanks in advance,

I am just getting started in digital design flow and in the process of bringing up a tsmc digital PDK. I am using genus and innovus v16.10 for synthesis and pnr. I have an understanding of the files that go into the process based on previous scripts available to me but would like a deeper understanding of what each of files do and how they work together. Where would be a good place to learn more?

Is there a difference between the digital qrcTechFile and the RF qrcTechFile?

Thanks 

Gabriel

Dear all, 

I have a design that is synthesized by Genus and I'm trying to auto-generate the layout using Innovus. 
Although the layout is auto-generated, the layout shows DRC violations. All violations are about "Metal Short" and only appear on the VDD net.

I'm assuming the tools are reading the rules from the technology lef file and should be able to generate a DRC-clean LVS-clean layout. 
Can someone help with this, please?

I have attached some screenshots from the layout and the Violation Browser window.  

Many thanks,

Anas

Hi,

When I run modus i face the following message:

Checking out license: Genus_Synthesis (13 seconds elapsed).
License 'Genus_Synthesis' (main version: 20.1, alternate version: 20.1) checkout failed.
Checking out license: Virtuoso_Digital_Implem (12 seconds elapsed).
License 'Virtuoso_Digital_Implem' (main version: 20.1, alternate version: 20.1) checkout failed.
Checking out license: Virtuoso_Digital_Implem_XL (12 seconds elapsed).
License 'Virtuoso_Digital_Implem_XL' (main version: 20.1, alternate version: 20.1) checkout failed.
Cannot obtain 'Genus_Synthesis' license.
Abnormal exit.

Does anyone have an idea why this is happening? or a recommendation to figure out why this is happening?

Dear community

I am using Innovus version 21.10 to implement a digital design in a 180nm process with 6 metal layers.
Layer 1,3,5 are horizontal routing layers, and layer 2,4,6 are vertical routing layers consequently. Layer 5 and 6 shall  be used exclusively for the power grid and power routing.
Currently, I am having the issue that the Special Route (sroute) seems to prefer using lower layers for routing e.g. PG-pins of IP blocks before connecting them to the power grid or power ring.s

Consider the following example: Here, an IP block called i0_xfab_mems/i0_XSPRAMVLP_512X22_M2P_ECC is surrounded by a power ring, which is located at layer 5 and 6. The PG-pins are on layer 3. Now I would like the tool to go to the 6th layer before routing to the nearby power ring, i.e. placing vias immediately on top or in front of the pins such that the space in front of the block can be used for routing. Note that the IP block has blockages up to layer 4 (not visible in the picture), but the blockage leaves enough space at the border such that nets and vias could be placed, theoretically.

The power ring was created using

innoivus > selectInst i0_xfab_mems/i0_XSPRAMVLP_512X39_M2P_ECC

innovus > addRing -nets {vddd vssd} -type block_rings -around cluster -layer {top MET5 bottom MET5 left METTP right METTP} -width {top 12 bottom 12 left 12 right 12} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 20 bottom 20 left 2 right 2}

and the stripes on top of the block were created with

innovus > addStripe -nets  {vddd vssd} -layer METTP -direction vertical -width pin_width -over_pins 1 -pin_layer MET3 -over_power_domain 1 -start_from left

The sroute command was executed as follows:

innovus > sroute -connect {blockPin} -blockPinTarget {blockring} -nets {vddd vssd} -blockPin all -deleteExistingRoutes -allowLayerChange 1

which yields the result in the picture above. If I now restrict the routing layers by setting -layerChangeRange {MET5(5) METTP(6)} the tool simply refuses to route any PG-pins. I have tried playing around with the layerChangeRange, blockPinLayerRange, crossoverViaLayerRange, and targetViaLayerRange argument, but none of these seem to make a difference.

How can I set a preferred rounting layer or force sroute to go to the two highest layers before doing any routing?

Thank you for any suggestions.

Dear all, 

I have a design on Innovus and I would like to take it to Virtuoso for verification.

What I found so far is that there are two ways to do it:

1. using GDSII + DEF files
2. using OA cell view.

Method 2 is recommended at different places, but when I try to save the design as OA library by: (File -> Save -> OA CellView) in Innovus, I have an error message telling me to check the log file (which I have checked and not much of info is there!).

Any suggestions on how to tackle this? 

Many thanks,

Anas

Dear all, 

I'm trying to import a layout from Innovus to Virtuoso as a GDS file. 

When I export the GDS file from Innovus, the following is shown: 

This clearly states that DBU is set to 2000 in the technology file (which I have verified and it is actually 2000 in the .lef file) and the generated GDS file has 2000 units per micron of precision, which sounds good! 

However, when I import the GDS file into Virtuoso, the log file shows the following warning: 

WARNING (XSTRM-284): DbuPerUU (1000) specified in the technology database or using '-dbuPerUU' is not divisible by the value (2000) set in the GDSII file. This can cause loss in data precision during translation.  

It says that there is a mismatch between DBU in GDS (2000) and the tech database (1000)! 

I have tried this solution to change the DBU stored for a library but I still have the same warning. 

Any idea on how to tackle it?

Many thanks

Anas 

Dear community

The SDC file I am using in my digital design has the two lines

set_units -capacitance 1000fF
set_units -time 1000ps

Reading this file into Innovus 21.10 leads to an "(TCLCMD-1461): Skipped unsupported command: set_units" error.

What is the correct syntax?

What are the default units in Innovus when nothing is specified?

Which command can be used to check what units are currently used (to verify that the timing analysis uses the right numbers)?

Thank you for any suggestions.

The commands I have used are as follows:

%addNet -power AVSS

%dbGet top.nets.name AVSS 

AVSS

%assignPGbumps -nets AVSS -selected

WARN(IMPSYC-1265): FTerm was not found for net "AVSS" ,AVSS has been created.

I dont understand the meaning of FTerm and (IMPSYC-1265)?

I would be very grateful if someone who  could advise me.