Dear community

I have a design containing two IP blocks which are connected with "critical high-voltage" nets. According to the datasheet, these nets need to be routed with a trace that is at least as wide as the corresponding pin (1.46 microns in this case) and coaxial shielding, that is, an additional trace towards ground placed to the left and right as well as a shield on top and bottom. The shielding can be minimum width with minimum spacing.

I create a non-default rule for the wider trace as follows:

Innovus > add_ndr -width {MET1 1.46 MET2 1.46 MET3 1.46 MET4 1.46 MET5 1.46 METTP 1.46 } -name 1_46w1s

The only way to assign shielding I could find in the manual is with nano route. Thus I set

Innovus > setAttribute -net myNet -shield_net vssd
Innovus > setAttribute -net myNet -non_default_rule 1_46w1s

Next, I run global and detailed route:

Innovus > selectNet myNet
Innovus > setNanoRouteMode -quiet -routeSelectedNetOnly 1
Innovus > routeDesign -globalDetail

This does not yield the wanted output yet.

Problem 1

This only creates a shield to the left and right of the net, but not at the top or bottom. There are three valid solutions:

1. Create the net on MET2/MET3 and place a shield on MET1/MET4
2. Create the net on MET1/MET2 and place a shield on MET3 only
3. Create the net on MET3/MET4 and place a shield on MET2 only (MET5 and MET6 are exclusively used for power routing only, i.e. there already is a "shield" on MET5)

How can I configure Innovus to create coaxial shielding according to the valid scenarios above?

Problem 2

Nano Route correctly uses the non-defailt rule to place a wider trace. However, sometimes the shield is not placed at all. I assume that Nano Route has some internal roules where it decides whether the shield can be placed or not. The problem here is that I actually need to run the Place and Early Global Route command before I am able to run Nano Route. As a result, there might be other nets routed nearby, thereby taking away the space that is needed to place a shield - at least that's what I believe is happening. Maybe a routing blockage would help here as a workaround. However, I would actually prefer to route those critical nets even before the placement step and then somehow lock them. Is there a way to manually place routes without relying on the Nano Route command?

Problem 3

Whenever Innovus performs a layer change on said critical net, only a single via is placed. How can I tell the tool to place as many vias as possible?

Thank you for any help.

Dear Community

I am working on a digital design where the I/O pads are placed in a predefined location. The floorplan is described in a .def file where the pads are defined as follows:

The numbers are made up; don't pay attention to them. Furthermore, the pins are simply placed on top of the I/O pads where their MET1 pin is located according to the LEF file. So for example:

PINS 256 ;
    - adc_in + NET adc_in
      + DIRECTION INPUT
      + PORT
        + LAYER MET1 ( 0 0 ) ( 280 280 )
        + FIXED ( 25 25) W ;
    - vddd + NET vddd
      + DIRECTION INOUT
      + USE POWER
      + PORT
        + LAYER MET3 ( 0 0 ) ( 280 280 )
        + FIXED ( 125 25) FN ;
    - vssd + NET vssd
      + DIRECTION INOUT
      + USE GROUND
      + PORT
        + LAYER MET3 ( 0 0 ) ( 280 280 )
        + FIXED ( 225 25) N ;
    - adc_out + NET adc_out
      + DIRECTION OUTPUT
      + PORT
        + LAYER MET1 ( 0 0 ) ( 280 280 )
        + FIXED ( 325 25) W ;
    < other definitions >
END PINS

Finally, the Pads are defined in the gate-level netlist from the synthesis tool, which looks something like this:

module pads(<long list of ports>);
    < other assignments >
    BBCUD4SF i0_BBCUD4SF (< pin assignment >);
    VDDPADF i0_VDDPADF (< pin assignment >);
    GNDORPADF i0_GNDORPADF (< pin assignment >);
    ICUDF i0_ICUDF (< pin assignment >);
endmodule

Now when I import everything into Innovus, the setup does not quite work yet. First of all, I get a warning that says

**WARN: (IMPFP-3961):    The techSite 'io_site_F3V' has no related standard cells in the LEF/OA library. The calculations for this site type cannot be made unless standard cell models of this type exist in the LEF/OA library. Ignore this warning if the SITE is not used by the library. Alternatively, remove the SITE definition for the LEF/OA library to avoid this message.

Could someone explain what a "site" is in this context?

Moreover, Innovus does not recognize the connection between the pads in the netlist and the floorplan. I get several messages in the form

IoPad I1 is not in DB, created it.
IoPad I2 is not in DB, created it.
IoPad I0 is not in DB, created it.
IoPad I3 is not in DB, created it.

As a result, Innovus places I/O Pads randomly in my design and links them to the pins defined in the .def file rather than using the predefined pads. Which steps are necessary such that Innovus makes the link between the netlist and the floorplan? Also, are there any special steps required for power pins?

Thank you for any advice.

Whenever I am restoring my design, I am getting an error message "ERROR: (IMPTR-2101):Layer M10: Pitch=11520x9 is still less than min width=32000 + min spacing=640".

The maximum defined metal layer in my tech file is till M9. But when I am running the command "generateTracks", it also generates M10. It's not affecting my flow but I just want to is there any solution to remove this error message.

I try to use "addstripe" command to add power net on ALPA,but its run so long(>24h),the detial as follows:

%setAddStripeMode -ignore_DRC true -respect_routes all -skip_via_on_pin {Pad Block Cover Standardcell Physicalpin} -skip_via_on_wire_shape {blockring stripe followpin corewire blockwire iowire padring ring fillwire noshape } -spacing_from_block 5

%addstripe -nets {VDD VSS} -layer ALPA -direction horizontal -width 10 -spacing 5 -number_of_sets 10  -set_to_set_distance 150 -start_from bottom -start_offset 242 -switch_layer_over_obs false -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit ALPA  -padcore_ring_top_layer_limit TM2  -block_ring_top_layer_limit ALPA  -block_ring_bottom_layer_limit TM2 -use_wire_group 0 -snap_wire_center_to_grid None

I guess some options I choose cause this dilemma?

By the way I have  exculded the influence of insufficient computing resources.

I will very appreciate it if someone can give me advise, thanks a lot.

Like the picture below, there are a lot of dangling wires related to the VSS and VSS. I am wondering whether there is a way to delete these wires nad solve these warnings. Thank you very much!

Dear all,

I currently have the layout now, and I am wondering whether there are some commands or steps that can help me futher improve the PPA of the layout (Especially the power and slack).

Thank you very much! 

Dear all, 

In my RTL design, I have VDD and VSS as inout ports to supply the core design with power (not sure if this is how ideally is done?). However, when I do the placement and routing of the layout, VDD and VSS pins are left unconnected, I would expect connections to be made from power pads to the power rings. 

Any idea why this is happening? 

I have attached my .tcl script file as well as the output log file from Innovus for your reference.

Many thanks,

Anas

Dear all,

I am seeking advice on how to efficiently assign different nets in my design to available pads so that they can be automatically routed using Innovus.

Presently, I am utilizing pins by placing them near the intended pads and then completing the net connections on Virtuoso. However, I am wondering if there is a more elegant way to perform this task in Innovus.

If you have any suggestions or recommendations, please feel free to share them.

Your assistance will be greatly appreciated.

Best regards,

Anas

Dear all, 

I'm using Innovus to place and route an RTL design synthesised by Genus.

After completing the routing, verify_drc tool highlights DRC errors on metal2 described as the following:

Special Wire of Net VSS & Blockage of Cell C48.

Actual: 0.028  Required: 0.6  Type: ParallelRunLength Spacing

The following are some screenshots from the layout: 

Can someone help me solve this, please? 

Many thanks,

Anas

Dear all, 

I'm working on Innovus to place and route a digital design generated by Genus. 

When I look at the auto-routed layout, there are some points at which I think the tool should be able to do a better job (if I correctly direct the tools). 

1) The Pad cells have two pins with the same name. The tool only connects one pin to the power ring. Is there a way to direct the tools to connect both pads? 

2) The strategy used to connect pad circuitry to PG nets is I think the "nearestTarget" strategy. Can I force the tool to use the nearestTarget everywhere except for PG nets, where I want all connections to be made directly to the power rings? 

sroute -connect { blockPin corePin padPin padRing floatingStripe } -layerChangeRange { M1 M5 } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -padPinTarget { nearestTarget } -corePinTarget { firstAfterRowEnd } -floatingStripeTarget { blockring padring stripe ringpin blockpin followpin } -allowJogging 1 -crossoverViaLayerRange { M1 M5 } -nets { VDD VSS } -allowLayerChange 1 -blockPin useLef -targetViaLayerRange { M1 M5 }

3) Should the PG and CLK signals be on a specific layer? I'm planning to have those signals on Metal5 as it should have the lowest capacitance in a 5M process, right? 

Please feel free to share your general advice to someone working on his first chip ^_^ 

Many thanks 

Anas

Dear all, 

I need some guidance on how to perform a proper timing analysis in Innovus to ensure all paths meet the performance requirements. 

First, in my Innovus scripts, I feed the design (.v file) and the constraints (.sdc file) which both are generated from Genus. I also use the .lib files of the STD cells to create an MMMC file and read it before initiating the design.

Then I run the following commands to perform timing analysis at different stages of the flow:

set_ccopt_property target_max_trans 0.294
set_ccopt_property target_skew 1

setCTSMode -engine ccopt

create_ccopt_clock_tree -name clk -source clk
ccopt_design

## report clock trees and skew groups
report_ccopt_clock_trees -file reports/$module/clock_trees.rpt
report_ccopt_skew_groups -file reports/$module/skew_groups.rpt

## report timing after CTS
report_timing -unconstrained -delay_limit 1 > reports/$module/timing_report_postCCopt.prt

However, when I check the Hold time (for example), the tool show (N/A) next to the timing value. I'm assuming that there is something wrong I'm doing.

Also, I'm not sure how to tell the tool that the 'clk' signal is a clock - not a normal input. How should I be defining the clock signal? Is it only through the .sdc file as it is currently done? Once I define the clock properly, will the tool automatically insert clock repeaters (or clock splitters) to meet timing requirements and prevent issues like clock skewing? 

Many thanks

Anas

-----------------------------------------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------------------------------------

The MMMC file: 

set lib /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcb018gbwp7t_270a

create_library_set -name fast\
-timing\
[list $lib/tcb018gbwp7tbc.lib]

create_library_set -name slow\
-timing\
[list $lib/tcb018gbwp7twc.lib]

create_constraint_mode -name my_constraint_mode\
-sdc_files /home/mchiama6/spiketrum/chip_m.sdc

create_rc_corner -name my_rc_corner\
-preRoute_res 1\
-postRoute_res 1\
-preRoute_cap 1\
-postRoute_cap 1\
-postRoute_xcap 1\
-preRoute_clkres 0\
-preRoute_clkcap 0\
-T 25\
-cap_table /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Back_End/lef/tcb018gbwp7t_270a/techfiles/captable/t018lo_1p5m_typical.captable\
-qx_tech_file /home/chip/qrcTechFile

create_delay_corner -name my_delay_corner_slow \
-library_set {slow} \
-rc_corner my_rc_corner

create_delay_corner -name my_delay_corner_fast \
-library_set {fast} \
-rc_corner my_rc_corner

create_analysis_view -name my_analysis_view_setup \
-constraint_mode my_constraint_mode \
-delay_corner my_delay_corner_fast

create_analysis_view -name my_analysis_view_hold \
-constraint_mode my_constraint_mode \
-delay_corner my_delay_corner_slow

set_analysis_view \
-setup {my_analysis_view_setup} \
-hold {my_analysis_view_hold}

-----------------------------------------------------------------------------------------------------------------------------

The .sdc file (Main commands):

# ####################################################################

# Created by Genus(TM) Synthesis Solution 21.10-p002_1 on Sat Mar 25 17:42:40 GMT 2023

# ####################################################################

set sdc_version 2.0

set_units -capacitance 1000fF
set_units -time 1000ps

current_design chip

create_clock -name "clk" -period 0.005 -waveform {0.0 0.0025}
group_path -weight 1.000000 -name C2C -from [list \
[get_cells {Subtractor/sig3_reg[5]}]

group_path -weight 1.000000 -name C2O -from [list \
[get_cells {Subtractor/sig3_reg[5]}] \
[get_cells {spike_generator_temp3_reg[2]}] ] -to [list \
[get_ports Con_Valid] \
[get_ports {Con_out[12]}] \
[get_ports {Con_out[11]}] \

group_path -weight 1.000000 -name I2C -from [list \
[get_ports clk] \
[get_ports reset] \
[get_ports IN_Valid] \
[get_cells RC_CG_DECLONE_HIER_INST/RC_CGIC_INST] ]

group_path -weight 1.000000 -name I2O -from [list \
[get_ports clk] \
[get_ports reset] \
[get_ports IN_Valid] \
[get_pins RC_CG_DECLONE_HIER_INST/enable] \
[get_pins RC_CG_DECLONE_HIER_INST/RC_CGIC_INST/E] ]
set_clock_gating_check -setup 0.0
set_clock_latency -max 0.005 [get_ports clk]
set_clock_latency -source -max 0.001 [get_ports clk]

-----------------------------------------------------------------------------------------------------------------------------

Dear Community

I use the following code in Innovus 21.10 to route a net called "VSE2" that is supposed to be much much wider than the remaining nets

add_via_definition -via_rule via1Array -row_col {3 3} -name via1_3x3
add_via_definition -via_rule via2Array -row_col {3 3} -name via2_3x3
add_via_definition -via_rule via3Array -row_col {3 3} -name via3_3x3
add_via_definition -via_rule via4Array -row_col {3 3} -name via4_3x3
add_ndr -name 1_46w1s -width {MET1 1.46 MET2 1.46 MET3 1.46 MET4 1.46 MET5 1.46 METTP 1.46} -via {via1_3x3 via2_3x3 via3_3x3 via4_3x3} -generate_via
setAttribute -net VSE2 -top_preferred_routing_layer 3 -bottom_preferred_routing_layer 2 -preferred_routing_layer_effort high -non_default_rule 1_46w1s
setNanoRouteMode -routeSelectedNetOnly true -drouteUseMultiCutViaEffort high
selectNet VSE2
routeDesign

This is the output:

Why is the right-hand side not routed correctly? What prevents Innovus from routing the net according to the NDR?

Thank you for any suggestions.

Platform: iMXRT500

SDK: SDK_2_11_1_EVK-MIMXRT595

Xtensa Xplorer IDE version: 8.0.15 Windows

I am trying to link SDK_2_11_1_EVK-MIMXRT595\CMSIS\DSP\Lib\GCC\libarm_ARMv8MMLldfsp_math.a to a DSP application. For this, in Xplorer IDE, I set the following:

Library search path is correct. But then, I still see this linker error:

C:/usr/xtensa/XtDevTools/install/tools/RI-2020.5-win32/XtensaTools/bin/xt-ld.exe: cannot find libarm_ARMv8MMLldfsp_math.a
make[1]: *** [dsp_hello_world_usart_fusionf1] Error 2

Please help.

Thank you,
Aravind.

Dear all, 

I'm trying to place bond pads into my design by following this solution.

What I did is the following: 

1- I have added the following at the top of my IO pad LEF file:

PROPERTYDEFINITIONS
    PIN bondPadOuter STRING;
    PIN bondPadMiddle STRING;
    PIN bondPadInner STRING;
    PIN ioCellOriginX REAL;
    PIN ioCellOriginY REAL;
    MACRO ioCellOffsetX REAL;
    MACRO ioCellOffsetY REAL;
END PROPERTYDEFINITIONS

2- In the definition of the MACRO that I am using, I added the following (the red text) in the PIN PAD section:

MACRO PDDW0208CDG
CLASS PAD ;
FOREIGN PDDW0208CDG 0.000 0.000 ;
ORIGIN 0.000 0.000 ;
SIZE 80.000 BY 120.000 ;
SYMMETRY X Y R90 ;
SITE pad ;
PIN PE
DIRECTION INPUT ;
PORT
LAYER METAL5 ;
RECT 66.730 119.000 68.730 120.000 ;
LAYER METAL4 ;
RECT 66.730 119.000 68.730 120.000 ;
LAYER METAL3 ;
RECT 66.730 119.000 68.730 120.000 ;
LAYER METAL2 ;
RECT 66.730 119.000 68.730 120.000 ;
LAYER METAL1 ;
RECT 66.730 119.000 68.730 120.000 ;
END
ANTENNAGATEAREA 5.1450 LAYER METAL1 ;
ANTENNAPARTIALMETALSIDEAREA 26.5212 LAYER METAL1 ;
ANTENNAPARTIALCUTAREA 0.2028 LAYER VIA12 ;
ANTENNAGATEAREA 5.1450 LAYER METAL2 ;
ANTENNAPARTIALMETALSIDEAREA 3.1800 LAYER METAL2 ;
ANTENNAPARTIALCUTAREA 0.2028 LAYER VIA23 ;
ANTENNAGATEAREA 5.1450 LAYER METAL3 ;
ANTENNAPARTIALMETALSIDEAREA 3.1800 LAYER METAL3 ;
ANTENNAPARTIALCUTAREA 0.2028 LAYER VIA34 ;
ANTENNAGATEAREA 5.1450 LAYER METAL4 ;
ANTENNAPARTIALMETALSIDEAREA 3.1800 LAYER METAL4 ;
ANTENNAPARTIALCUTAREA 0.3888 LAYER VIA45 ;
ANTENNAGATEAREA 5.1450 LAYER METAL5 ;
ANTENNAPARTIALMETALSIDEAREA 14.0400 LAYER METAL5 ;
END PE


PIN PAD
DIRECTION INOUT ;
PORT
LAYER METAL5 ;
RECT 4.900 0.000 75.100 4.870 ;
LAYER METAL4 ;
RECT 4.900 0.000 75.100 4.870 ;
LAYER METAL3 ;
RECT 4.900 0.000 75.100 4.870 ;
LAYER METAL2 ;
RECT 4.900 0.000 75.100 4.870 ;
END
ANTENNAGATEAREA 14.4000 LAYER METAL2 ;
ANTENNADIFFAREA 1914.0232 LAYER METAL2 ;
ANTENNAPARTIALMETALSIDEAREA 823.5882 LAYER METAL2 ;
ANTENNAPARTIALCUTAREA 39.7488 LAYER VIA23 ;
ANTENNAGATEAREA 14.4000 LAYER METAL3 ;
ANTENNADIFFAREA 1914.0232 LAYER METAL3 ;
ANTENNAPARTIALMETALSIDEAREA 79.5742 LAYER METAL3 ;
ANTENNAPARTIALCUTAREA 72.4672 LAYER VIA34 ;
ANTENNAGATEAREA 14.4000 LAYER METAL4 ;
ANTENNADIFFAREA 1914.0232 LAYER METAL4 ;
ANTENNAPARTIALMETALSIDEAREA 79.5742 LAYER METAL4 ;
ANTENNAPARTIALCUTAREA 34.7328 LAYER VIA45 ;
ANTENNAGATEAREA 14.4000 LAYER METAL5 ;
ANTENNADIFFAREA 1914.0232 LAYER METAL5 ;
ANTENNAPARTIALMETALSIDEAREA 351.3276 LAYER METAL5 ;
PROPERTY bondPadOuter "PAD80LU_TRL" ;
PROPERTY bondPadMiddle "PAD80LU_TRL" ;
PROPERTY bondPadInner "PAD80LU_TRL" ;
PROPERTY ioCellOriginX 25.0 ;
PROPERTY ioCellOriginY 0.0 ;
END PAD


PIN OEN
...
END OEN


PIN IE
...
END IE


PIN I
...
END I


OBS
...
END


END PDDW0208CDG

3- I tried to run the following command after completing placement and routing: 

placeBondPad -ioInstName B22 -pad PAD80LU_TRL -pinName PAD -position o

B22: the instance name of the IO cell (instance of PDDW0208CDG).

PAD80LU_TRL: is the macro used for the bonding cell.

However, the following error message is shown: 

ERROR: (IMPSYC-1142): Cannot find IO Instance 'B22'.

I'm sure that the B22 exists in the design, and it is defined in the IO frame file as:

(inst name="B22"  cell=PDDW0208CDG place_status=fixed ) 

 Any idea which part I did wrong?

The definition of PAD80LU_TRL is:

MACRO PAD80LU_TRL
CLASS BLOCK ;
FOREIGN PAD80LU_TRL 0.000 0.000 ;
ORIGIN 0.000 0.000 ;
SIZE 80.000 BY 81.000 ;
SYMMETRY X Y R90 ;
OBS
LAYER METAL4 ;
RECT 0.000 0.000 80.000 81.000 ;
LAYER METAL5 ;
RECT 0.000 0.000 80.000 81.000 ;
END
END PAD80LU_TRL

Many thanks,

Anas

I have generated synthesized netlist of my verilog design on Synopsys Design Compiler tool. For post layout results, Cadence Innovus tool was used and .spef file was generated. When this .spef file is used in Synopsys Primetime PX tool, some nets and pins are not recognized.

The errors are mentioned in detail in the attached log file.

community.cadence.com/.../parasitics_5F00_command.log

Dear community

Our design has three main clocks. Let's call them clk1, clk2, and clk3. Each clock has several child clocks running at the same frequency. So the SDC file could look like this:

create_clock -name "clk1" -period 62.5 -waveform {0.0 31.25} [get_ports clk1]
create_clock -name "clk2" -period 250.0 -waveform {0.0 125.0} [get_ports clk2]
create_clock -name "clk3" -period 83.3 -waveform {0.0 41.65} [get_ports clk3]

create_generated_clock -name "clk1a" -divide_by 1 -source [get_ports clk1]   [get_pins clk1a]
create_generated_clock -name "clk1b" -divide_by 1 -source [get_ports clk1]   [get_pins clk1b]
create_generated_clock -name "clk1c" -divide_by 1 -source [get_ports clk1]   [get_pins clk1c]
...

create_generated_clock -name "clk2a" -divide_by 1 -source [get_ports clk2]   [get_pins clk2a]
create_generated_clock -name "clk2b" -divide_by 1 -source [get_ports clk2]   [get_pins clk2b]
create_generated_clock -name "clk2c" -divide_by 1 -source [get_ports clk2]   [get_pins clk2c]
...

create_generated_clock -name "clk3a" -divide_by 1 -source [get_ports clk3]   [get_pins clk3a]
create_generated_clock -name "clk3b" -divide_by 1 -source [get_ports clk3]   [get_pins clk3b]
create_generated_clock -name "clk3c" -divide_by 1 -source [get_ports clk3]   [get_pins clk3c]
...

The child clocks are, logically, synchronous to their parent clock and thus to other child clocks derived from the same parent clock, but asynchronous to child clocks from other parent clocks. So for example, clk1 and its childs clk1a, clk1b, clk1c, ... are asynchronous to clk2 and clk3 including their children. Vice versa, clk2 and clk3 are asynchronous to clk1 and its children. Same is true between clk2 and clk3.

How can I constrain this without having to write down every single combination?

Hello All,

Dear community

Please consider the following design:

The design has two operational modes, and depending on which mode it is, the input port sclk serves a different purpose. Let us call those modes Mode A and Mode B.

• In mode A, the input sclk serves as a clock input. Here, the output if_sclk of the module i0_ctrl is active. if_sclk is a gated clock running at the same frequency as sclk, i.e. the tool (Innovus 21.10 in my case) is supposed to create a clock tree on this net.
• In mode B, the input sclk serves as a normal data input. Here, the output test_data of the module i0_ctrl is active. This signal is used by some logic that is synchronized to the internal main clock clk.

The two outputs of the module i0_ctrl are exclusive, i.e. only one of them can be active at any time. Which operational mode is used is controlled by external signals (not relevant for this question). The two clock domains sclk and clk are asynchronous. The pad has a serial resistor and some protection components. That's why the internal net (sclk_in) has a different name.

Here is how I would write a minimal SDC file:

SDC File for Mode A

create_clock -name "clk" -period 62.5 -waveform {0.0 31.25} [get_ports clk]
create_clock -name "sclk" -period 250.0 -waveform {0.0 125.0} [get_pins i0_pad/Y]
create_generated_clock -name "if_sclk" -divide_by 1 -source [get_pins i0_pad/Y] [get_pins i0_ctrl/if_sclk]
set_clock_groups -asynchronous -group {clk} -group {sclk if_sclk}

SDC File for Mode B

create_clock -name "clk" -period 62.5 -waveform {0.0 31.25} [get_ports clk]
set_input_delay -clock [get_clocks clk] -add_delay 20.0 [get_ports sclk]

Whether this is correct or not I do not know; I was unable to find a simiar example in manuals. Here are some questions that came up:

1. How to correctly define gated clocks? Is the approach with create_generated_clock correct?
2. To what object should the clock sclk be assigned in Mode A? The port? The input or output pin of the pad? The pin of the module i0_ctrl?
3. How do I constrain the port if_sclk in Mode B? This net technically still is a clock net in Mode B; it just does not have a driver that generates an actual clock, i.e. all connected logic is inactive. Can I just leave this black or do I need to specify it as a clock anyway? I tried both variants. Boch can be imported into Innovus without generating errors, but the resulting clock tree is different and I do not know which one is correct.

Thank you very much for any suggestions.

Hi All,

I get four violations in wiring (shorts) in the sign off stage of pnr. When I run the drc on the generated layout it comes out to be clean.

I have a few queries:

1. How do I check which nets are short?

2. How do I fix these violations?

3. If drc is clean (I run drc on generated layout using calibre), should I be worried about the functionality of my design?

Dear all, 

When I use the sRoute command to connect the PG rails, sRoute dosn't connect the rails to the PG ring, instead it stops routing at the core boundary, as shown below:

Is there a way to fix this and make it starts and finishes at the PG rings? The VerifyConnectivity sees those rails as antenna violations. 

The command I'm using:

sroute -nets {VDD VSS} -connect {padPin} -padPinTarget {ring} -padPinPortConnect {allPort allGeom}

Kind regards,

Anas