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Large difference between post-route and signoff timing despite up-to-date RC scaling factors

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Dear Community

I have a design whose timing is fulfilled at the post-rouote stage. If I run

setExtractRCMode -engine postRoute -effortLevel high
timeDesign -postRoute -setup -hold

I get the following result.

+--------------------+---------+---------+---------+---------+
|     Setup mode     |   all   | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
|           WNS (ns):|  0.000  |  0.000  | 18.512  |  0.164  |
|           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |
|    Violating Paths:|    0    |    0    |    0    |    0    |
|          All Paths:|  20636  |  20141  |   32    |  6271   |
+--------------------+---------+---------+---------+---------+

+--------------------+---------+---------+---------+---------+
|     Hold mode      |   all   | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
|           WNS (ns):|  0.046  |  0.046  |  0.648  |  3.356  |
|           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |
|    Violating Paths:|    0    |    0    |    0    |    0    |
|          All Paths:|  20636  |  20141  |   32    |  6271   |
+--------------------+---------+---------+---------+---------+


However, If I run

timeDesign -signoff -setup -hold

I get a much worse result:

+--------------------+---------+---------+---------+---------+
|     Setup mode     |   all   | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
|           WNS (ns):| -9.366  | -9.366  | 18.545  |  0.223  |
|           TNS (ns):| -27.222 | -27.222 |  0.000  |  0.000  |
|    Violating Paths:|   31    |   31    |    0    |    0    |
|          All Paths:|  20638  |  20143  |   32    |  6271   |
+--------------------+---------+---------+---------+---------+

+--------------------+---------+---------+---------+---------+
|     Hold mode      |   all   | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
|           WNS (ns):|  0.002  |  0.002  |  0.644  |  3.374  |
|           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |
|    Violating Paths:|    0    |    0    |    0    |    0    |
|          All Paths:|  20636  |  20141  |   32    |  6271   |
+--------------------+---------+---------+---------+---------+

According to the manual, this can happen due to bad correlation between the post-route RC scaling factors and the signoff extractor. Thus, I updated the RC factors with

generateRCFactor -preroute true -reference signoff -outputFile update_preRoute_RC_scale_factors.tcl
generateRCFactor -preroute false -postroute medium -reference signoff -outputFile update_postRoute_RC_scale_factors.tcl
source update_preRoute_RC_scale_factors.tcl   # At the beginning of the flow
source update_postRoute_RC_scale_factors.tcl  # After routing

and restarted the flow, but the result is almost the same.

At the sign-off stage, only two paths have a much worse timing. The other 29 violating paths have a very small negative slack of a few ps. To further debug the proble, I compared the worst path (according to the signoff timing) to the same path with post-route timing. Here is the output of said path in the signoff stage:

Path 1: VIOLATED Data To Data Setup Check with Pin i0_elisa_digital_top/i0_nv_
mem/i0_XNVR_2KX8P2016_VW01C/HS
Endpoint:   i0_elisa_digital_top/i0_nv_mem/i0_XNVR_2KX8P2016_VW01C/MEM_ALLC     
(^) checked with  leading edge of 'clk'
Beginpoint: i0_elisa_digital_top/i0_elisa_digital_core/i0_nv_mem_ctrl/i0_nv_mem_
access/mem_allc_cs_reg/Q (^) triggered by  leading edge of 'clk'
Path Groups: {clk}
Analysis View: slow_normal_mode_vtx
Other End Arrival Time          4.133
- Data Check Setup              5.000
+ Phase Shift                   0.000
+ CPPR Adjustment               1.221
- Uncertainty                   3.000
= Required Time                -2.646
- Arrival Time                  6.720
= Slack Time                   -9.366
     Clock Rise Edge                 0.000
     + Clock Network Latency (Prop)  0.830
     = Beginpoint Arrival Time       0.830

And when I use the same command (report_timing -from <startpoint> -to <endpoint>) at the post-route stage, I get:

No constrained timing paths with given description found.
Paths may be unconstrained (try '-unconstrained' option) or may not exist.

How can that be? According to this document, above's report can happen e.g. when timing checks are disabled, the path is constrained as static, etc., none of which is the case in our design (we only constrain top-level pins, no internal pins).

1. How can it happen that a path is unconstrained at the post-route stage, but constrained in the signoff stage?

2. I noticed that the RC scaling factors are quite close to 1 and even smaller than one in most cases. Intuitively, I would expect them to be larger than one. Might there be something wrong with how I generate them? Here are the generated post-route RC scaling factors:

update_rc_corner -name RC_typ_T25 -postRoute_cap {0.924 0.953 } -postRoute_res {0.997 0.969 } -postRoute_xcap {1.050 0.964 } -postRoute_clkcap {0.799 0.893 } -postRoute_clkres {0.996 0.978 }
update_rc_corner -name RC_min_Tm40 -postRoute_cap {0.925 0.969 } -postRoute_res {0.998 0.971 } -postRoute_xcap {1.032 0.966 } -postRoute_clkcap {0.800 0.909 } -postRoute_clkres {0.997 0.980 }
update_rc_corner -name RC_max_T125 -postRoute_cap {0.929 0.954 } -postRoute_res {1.006 0.964 } -postRoute_xcap {1.029 0.964 } -postRoute_clkcap {0.798 0.891 } -postRoute_clkres {0.999 0.974 }

Thank you for any suggestions.


Cadence Modus generated test pattens

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In the test pattern file generated by Modus tool in stil format, I wish to know what are the test patterns assigned to the PI and PPI.

Example (from the stil file)-


//***************************************************************************//
//  TEST SEQUENCE.............3        TYPE......................normal      //
//***************************************************************************//

//  Processing the Static: EVENT 1.2.1.2.2.1.1;  Scan_Load;  (no_overlap)
// Inserted the Scan Sequence:  Scan_Preconditioning_Sequence  
//  Inserted the Static: EVENT Stim_PI;
  Macro "TEST" {
    "ALLPIs" = 1000000;
    "ALLPOs" = XXX; }
// Inserted the Scan Sequence # 3;  Scan_Sequence  
  Macro "SCAN_TM_1" {
    "CR_1_TM_1" = 1001 \r8 0 ; }

//  Processing the Static: EVENT 1.2.1.2.2.2.1;  Stim_PI;
  Macro "TEST" {
    "ALLPIs" = 0101101;
    "ALLPOs" = XXX; }
//  Processing the Static: EVENT 1.2.1.2.2.3.1;  Measure_PO;
  "1.2.1.2.2.3":
  Macro "TEST" {
    "ALLPIs" = 0101101;
    "ALLPOs" = LHH; }
//  Processing the Static: EVENT 1.2.1.2.2.4.1;  Scan_Unload;  (no_overlap)
  "1.2.1.2.2.4":
// Inserted the Scan Sequence:  Scan_Preconditioning_Sequence  
//  Inserted the Static: EVENT Stim_PI;
  Macro "TEST" {
    "ALLPIs" = 1101101;
    "ALLPOs" = XXX; }
// Inserted the Scan Sequence # 4;  Scan_Sequence  
  Macro "SCAN_TM_1" {
    "OR_1_TM_1" = HLLH \r8 L ; }

In the test patterns, can I generate patterns with don't care (without filling the don't care bits with 0 or 1)

Xtensa TIE documentation

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Hi,

Could you please tell me where I can find the documentation for the Xtensa TIE and FLIX? As all your documents refer to following documents, however none of them is available on your website, any URLs that I find leads to some broken redirects on your webpage.

  • Tensilica Instruction Extension (TIE) Language User’s Guide
  • Tensilica Instruction Extension (TIE) Language Reference Manual.

For example this documents mention it:

https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/tensilica-ip/tip-tie-wp.pdf

https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/tensilica-ip/hw-dev-wp.pdf

Instance Padding

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Hi everyone,

Is there any way to force instance padding won't honor physical_only instance?

Thanks

*** CRASHED *** [signal 11] Segmentation fault (core dumped) invoking tempus

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what can be the problem?

i run tempus 

it gives me this warning

**WARN: (IMPOAX-1142): Current Tempus Timing Signoff Solution hierarchy has cds.lib plug-in installed and both cds.lib & lib.defs files are present in the current directory. The cds.lib file will be used. The lib.defs file will be ignored and it will not be updated.


and then it crashes 

Using the generic PDK with Genus

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Hello all,

I'm quite new to using the Cadence software suite so my question might be a bit naive or easily answered.

I'm working at an educational facility and I was asked to see if the Cadence generic PDK (45nm) can be used with Genus. The students are supposed to synthesize an open microcontroller design, work on optimization and verification before presenting the results. Basic tasks for them to work with professional software. The next course is supposed to work with just the generic 45nm PDK from Cadence instead of the very old libraries we have now.

I downloaded the PDK, unpacked it but none of the .lib files are accepted by Genus. From the thread https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/48008/generating-lib-file-for-synthesis-using-genus-from-transistor-level-cells-using-virtuoso I get the idea that I need to get the post-synthesis netlist and combine them with the models from the gPDK to get a combination that Liberate can use to generate the .lib file.

The point that I'm having trouble with is getting the netlist in the first place. As far as I understood the software suite Genus is used to synthesize verilog designs and generates the netlist, but I cannot use Genus because I don't have the lib file.

Is there a generic way to get to get the lib file or at least a way that is specific for the design we are using?

Thank you in advance!

Verilog netlist to Schematics

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Dear all, 

I have an RTL design synthesized by Genus, and placed and routed by Innovus.

In the process of verifying the design, I was thinking of running Corner Analysis. I have done such analysis before using Virtuoso for a schematic view design. 
So, I started thinking about how I could convert the netlist generated by Genus to a schematic that I could open in Virtuoso and run the different simulations. 
I tried using the Verilog In tool in Virtuoso (File -> Import -> Verilog) but that didn't quite work.

Any suggestions? Many thanks.

Kind regards,

Anas

AI affects

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How AI is affecting your corporate life?


New versions of GENNUS and INNOVUS not running on CentOS 9

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We recently upgraded from CentOS 7 to CentOS 9. IC618, SPECTRE, GENUS152 work fine. 

GENUS 211(Aug. 2023 version) and INNOVUS211(Aug. 2023 version) do not start. The output is given below. It is not clear if it related to checkSysConf or lack of lsb_release because Virtuoso also gives the same warning when invoked, but runs nonetheless.

test_user@ams194~/Digital_Synthesis/synthesis> 143: genus
2023/09/02 20:22:49 WARNING This OS does not appear to be a Cadence supported Linux configuration.
2023/09/02 20:22:49 For more info, please run CheckSysConf in <cdsRoot/tools.lnx86/bin/checkSysConf <productId>
WARNING: not possible to detect OS, missing lsb_release command!
test_user@ams194~/Digital_Synthesis/synthesis> 144:

I did search for posts related to lsb_release but they seem to complain about none of the tools running. (example below). Any help would be appreciated. 

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/57414/cannot-install-cadence-ic618-on-rhel-9

Regards

Nagendra

innovus placement related issue

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Dear all,

I have two questions:

(1) I am wondering if innovus has the function of global placement, which is w/o legalization.

(2) Can I costumize the goal of legalization? Or its cost function is fixed?

I have found so long, and still having no idea.

Thank you very much!

The .def file after placement stage

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Dear all,

After the place_opt stage, I output the def file and I see that there are NETS part in the def file. Is it normal that before the routing stage? Thank you very much!

Best regards

Power estimation of combinational logic design in Genus

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While performing logic synthesis of a combinational logic design, I observed that Joules does not use the switching activity information from a VCD or TCF file provided for power estimation in Genus. Joules performs vectorless power computation. Is there an option to override vectorless computation settings and use switching activity information for a combinational logic design synthesis in Genus? I am using Genus_Synthesis 19.1.

How do I exclude specific cells of the library?

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I don't want to use few cells like AO, MUX from my technology file, for example    tcbn65gplusbc/AO* tcbn65gplusbc/BEN* tcbn65gplusbc/BHD*

What is the script for doing it?

I tried set_attribute [get_cells {cellName1 cellName2 ...}] dont_use true
But it is not working!

Version: SoC Encounter RTL to GDSII system 8.1

VOLTUS_RAIL-4084: Hierarchy PGV cell has a misformatted connection because of an extra delimeter ":'

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As a result of extra delimeter hierarchical rail analysis is failing and when we traverse through the block ,rail analysis is a perfect pass

find cells in row next to all same

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I have special capacitor cells in layout.  sometimes they abut next to each other in cell row.  Need to find all the places where there are many of these next to.  When find them,get the X1 X2 of where they are in a row.  How to complete task?


write placement blockage around cell

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I have special placed cell.  I need to find cell and draw placement blockage for full width of cell for the complete height of the design.  From top to bottom of the design.  How to complete task?

Stylus Flowtool Logfiles/History

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Hi everyone,

I currently started using Stylus Flowtool for my digital workflow. I am struggling with the infinite amount of logiles it creates (.log, log1,.... .logx) for each tool and step. Innovus also does not overwrite it's outputs but instead again creates a new view every time (cts_block_finish, cts_block_finish1...).

Is there a way/command to tell flowtool to overwrite both the old logfiles and results of each step when re-running it?

Thanks,

Kim Allinger

Genus crash- generate_ilm

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Hi, 

I am working on a significant design, running synthesis for each sub-block. I generate an ILM (Interchange Logic Model) for each sub-design. However, when I attempt to run 'generate_ilm' for one of the designs, the tool crashes with the following message:

"
Transforming the design design:RocketTile into ILM  
Segmentation fault (core dumped)
"

What could be the problem? I don't have a stack trace file for the crash, and the design (RocketTile) is relatively small with nothing particularly unique about it. Additionally, it's worth noting that the tool crashes only for this specific design, as it works fine with other designs.

Innovus - Layout View (vs abstract/black-box view)

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Dear all, 

I used Innovus to auto place and route a digital design (synthesized by Genus). However, when I look at the generated layout, it doesn't show the layout view of the cells (not even the abstract view). To me, this is like a black-box view. Please see the image below. Is there a way to tell Innovus to use the layout view for the standard cells? Shouldn't this also affect the DRC? I have verified that I have access to the layout view through Virtuoso. 

I'm using TSMC180. 

Kind regards,

Anas

New Pelle Pelle Jackets

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