Tran On Clock!

Hi Folks!

I'm seeing huge numbers of tran violations on the clock nets in my design. Can anyone kindly explain as how to approach this problem?.. How do I fix these?... Is the problem with CTS not building the clock properly?.. Tran on the clock nets is likely to violate hold right?...

I'm setting the max tran for all the clocks in my  sdc as 100ps and the worst violation is  -240ps on the clock net.

Kindly provide some insight into this.

Thanks In advance!

JK