6T Bitcell characterization using Encounter Library Characterizer

Hi everyone.

I'm trying to characterize a 6T sram bit cell using Encounter Library Characterizer but unfortunately I can't generate a verilog of this cell. The alf2veri routing reports the following error:

CELL BITCELL6T:
  now reading
  now converting
[ERROR(alf2veri)] behavior is empty

When I look into the gate files, this cell was sucessfully recognized :

DESIGN ( BITCELL6T );
//      =================
//       PORT DEFINITION
//      =================
        INPUT BIT_IO ( BIT_IO );
        INPUT BIT_N_IO ( BIT_N_IO );
        INPUT WORD_LINE_I ( WORD_LINE_I );
        SUPPLY0 GND ( GND );
        SUPPLY1 VDD ( VDD );
        -COMPLEMENTARY ( BIT_IO, BIT_N_IO );
//      ===========
//       INSTANCES
//      ===========
        NOT ( Q, QN );
        IMUX ( QN, WORD_LINE_I, BIT_IO, Q );
END_OF_DESIGN;

Besides the boolean file reports the following logical structure:

BITCELL6T
,       REGISTER([QN],[Q])::=(~(WORD_LINE_I?BIT_IO:[Q]),~(WORD_LINE_I?BIT_IO:[Q]))
;
The behavior of this cell depends on the load so it is really hard to model it in verilog. However there must be an easy way to do it.

Thanks