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command for renaming pin name of blackbox
Hi,I compare RTl vs RTL using con-formal. I created black box for IP in RTL and I did mapping but few signals are not mapped due to different name. How to change "pin name" of black box.
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Is it possible to import and simulate in virtuoso without the exact GDS info...
Hello everyone,For the standard cell library I was provided with, I have the following files:1. .lib files(worst,best,typ etc.) 2. .v file (verilog description of the std cell library) 3. .lef file...
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Macro Placement Issue with Custom LEF file
Hi all,I have a macro that is essentially a special-via (two metal layers connected through a cut layer). My netlist includes several of these macros as physical-only cells defined in a LEF file with...
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Auto complete tab not work
Dear All,There are some pre-defined procs that I could not use tab to auto complete, but some procs can work. I used innovus shell prompt.Could anyone tell me why and how to use them normally? Thanks...
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NCVLOG error NPITEM -- Not a valid package item: 'interface_declaration'...
Hi,I am trying to compile a design with Incisive, using "irun" commands.The design was previously compiled and tested with VCS.When compiling some VIPs, I encountered multiple times the following...
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Compilation Errors for UVM constructs using xcelium
Hi,I will shortyly tell the problem:The following code line :if(!$cast(tmp,rhs))`uvm_fatal(get_type_name().toupper(), "Type mismatch")...
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SRAM Design
I am designing a SRAM cell in 45nm technology. For reading and writing i am designing the complete circuit using a precharge, write driver and sense amplifier. When I an activating the precharge...
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Placement algorithm that used in SOC Encounter
Hi all,I am relatively new to the Encounter tool. I am using Encounter v6.2 to place a simple design.I have a question about the Place & Route Algorithm that used in this software.I want to know,...
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Static Rail Analysis Problem
Hello,I am doing a static rail analysis for a small design. I am getting a following error and warning in-spite of properly defining the proper power pin, power net, ground pin and ground net:Analyze...
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GPDK045: QRC Extraction fails with Innovus v16.13-s045_1
Hello,I am using the GPDK045, but Innovus segfaults upon RC extraction. Maybe I have set up something wrong?My RC Corner is:create_rc_corner -name rc_corner\-cap_table...
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Innovus Common UI
Hello There!Just a very brief question. There is a very nice command in Genus to report runtime and memory usage - "time_info". I am looking for something similar for Innovus ( common ui ).Thanks and...
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Metal-layer Cells
Hi All,I have special devices that similar to vias lie between two metal layers (think about a metal-insulator-metal capacitor, a metal-to-metal fuse, or a component similar to that). The device is...
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ccopt ignore sink - common ui
Hello,I am looking for a way to remove several sink points from the list of CCOPT leafs, to make sure it will not build the clock tree to these pins.Thanks and regards,Boris
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Core filler not getting inserted below vertical power stripe
I am using Innovus Implementation system V15.20 for my design flow, My design contains custom made cells for which lib and lef file has been generated manually (using liberate and abstarct tool...
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Missing libraries when running Innovus Clock Tree Synthesis
Hello,I'm running innovus 16.2 on Linux Centos 6.I've got a problem at clock synthesis stage when instanciating buffer and etc ... It prints the message : **ERROR: (IMPCCOPT-3092): Couldn't load...
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Level-shifter cells are removed after placement
Hi there!In my design, I intend to have a power domain containing all level-shifter cells.The steps I have taken towards this target:1- using a clock buffer as the level-shifter component in...
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I/O pad pins are placed randomly (each pad_pin is not placed on the...
Hi all,in Innovus 16.2, after "init_design", the I/O pads' terminals are not placed on the corresponding pad. Does anybody have had similar problems? or any clue about this?As you can see in the...
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tie cell net connection missing
Why Tie Cell connections are missing in the instantiated module in the final PNR Verilog netlist, Module declaration in the final netlist has tie cell connections but the instantiated cell doesn't show...
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Generating ITF file from ICT file?
Building a new flow that involves StarRC and wanted to understand if there was any recommendations of converting an ICT file into the ITF files using as the source for StarRC's reference files? From...
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CPF - two primary_power_nets for one power domain (different virtual power...
Hi there!Cadence innovus 16.13 | CPF v1.1 | ST Microelectronic 28nmI am working on a Multiple power domain design. I have got a PLL block as an IP (no access inside the block of course) and this PLL...
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