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Digital implementations make games easier to grasp ?

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I thought of that because I bought the Friday app after losing 7 times. I won my first 2 digital games, and I can't seem to stop winning even after coming back to the physical version (gotta bump the difficulty now, hehe).

I felt the same about Terraforming Mars: even if I was already pretty good before and I only played against the bots (even the hard ones are not a big challenge), it seemed to me that I bought fewer useless cards during games and I was more focused on my strategy. It also was still the case for my future physical multiplayer plays.Overall it seems like those digital implementations help me take a step back to analyze the game and become a better player, and I wondered if you had similar experiences. (It might not always be true though, I'm still pretty bad at Coffee Roaster)

Thanks for your answers!


Mesh router: discover the benefits of wi-fi technology

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Have a fast internet available in all corners of the property with the same signal strength, bringing a higher quality than that offered by wi-fi repeaters . This is what the Mesh router offers , technology that has gained more and more prominence.

With the number of connected devices increasing, it is essential to have a stable connection in all environments, because only then will you be able to play games, watch movies and series , do research, turn on or off smart devices and perform other tasks without suffering from signal loss .

However, even if the fixed broadband contracted is of high speed, some areas of the house may have a weak signal or not even receive it, depending on the distance and characteristics of the environment, when using a conventional router.

If this is the case, it is worth knowing the Mesh router, which can become a good alternative for those who have many devices connected at home and suffer from wi-fi problems .

What is Mesh technology?

Widely used in the United States, Europe and Asia, Mesh technology uses two or more modules scattered around the property and connected to a compatible router to form a high-quality Wi-Fi network .

Connected to each other, these devices form a mesh (hence the name Mesh) capable of covering the entire area of ​​the residence, distributing the wireless signal equally, without losing power.


Unlike repeaters, the Mesh network modules have no amplification limit and work dynamically and intelligently, eliminating blind spots that had no connection because of the distance from the signal source and the existence of obstacles (furniture and walls).

Depending on the size of the property, only one Mesh router can handle the distribution. But, in case it is necessary to expand the coverage, it is enough to acquire more modules and install them in strategic locations.

Is there a way to name matrixial instances or nets?

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Hi all.

Does anyone know if I could name matrixial instances or nets?

For instance:

I<i,j> or net<i,j>

Thanks in advance

Jorge

Global net connections warning on export netlist with power pins for block implementation

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Hi,

I am running a digital implementation using Innovus v18.10-p002_1. It is a digital block with only one supply voltage. The top will be done on Virtuoso (with addition of PADs over there). In other words, my Verilog has no PADs.

The implementation go smoothly, I used a CPF to define the power domain and connect cells to the global nets. But when I try to export the netlist with power pins, I have many warnings like the one below. I checked the design from every possible perspective, and I could not find any mistake. My flow looks correct (I tried multiple alternatives with same result) and the database is consistent (all pins in all instances are connected to the global power nets VDD/VSS). The generated netlist is also correct, as far as my simulation can test. But those warnings are a bit scary.

Are these warnings expected for a block level design without PADs when exporting a netlist with power pins?

Thanks a lot for the support!

@innovus > write_netlist -phys top.v
Writing Netlist "top.v" ...
Pwr name (VDD).
Gnd name (VSS).
1 Pwr names and 1 Gnd names.
**WARN: (IMPVL-531): None of the instances inside cell/module 'MODULE_NAME1...' has power/ground connections, likely because global net connections (from globalNetConnect or CPF) have not been applied to the instances. Make sure this is acceptable, or apply the needed GNCs/CPF to make the required power/ground connections and re-save the netlist.
**WARN: (IMPVL-531): None of the instances inside cell/module 'MODULE_NAME2...' has power/ground connections, likely because global net connections (from globalNetConnect or CPF) have not been applied to the instances. Make sure this is acceptable, or apply the needed GNCs/CPF to make the required power/ground connections and re-save the netlist.

...

Innovus - Poly alignment issue

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Hi
After the placement stage in the innovus, I could see the polys of the placed standard cells misaligned. Please see the screenshot below. This is causing many DRC violations when the GDS is imported in virtuoso . What could be causing this issue and how can we solve this?  Any help is greatly appreciated.
Thanks in advance
regards
Shreyas

Capacitor Array

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Hi,

I am trying to create a capacitor array in Innovus that is 8 cells in height and 32 cells in width. There is an issue once I read the Verilog netlist and place the design where the elements are completely randomly placed on the layout. An example is cell C0 (capacitor 0) has C129 (capacitor 129) stacked on top of each other. Ideally, I would like the left most of the design to start with an 8-cell stack from capacitors C0-C7. Then the next column would have capacitors C8-C15 and so on. Is there a way to ensure that the cells are placed in such a fashion?  

Restrict buffer use for a particular sub block while routing using INNOVUS

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Is it possible to route clock tree with up to 8x buffers for everything except one particular sub block where buffers larger than 4x are not used? 

VHDL IEEE Library not recognized by RTL Compiler or Genus

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Hello,

I guess this is a dumb question but I didn't find any having the same issue as mine or any tutorial to guide me through this process...

I wanted to synthesize a design written in VHDL with either RC or Genus, but I got the same error (and the error repeats for each VHDL file...)

library IEEE;
        |
Error : Missing token. [VHDLPT-672] [read_hdl]
: library clause requires ';', read <identifier> IEEE in file 'addroundkey.vhd' on line 46, column 9.

I guess I need to explicitly point to the IEEE library, which I am not sure how to do. Any insight would be greatly appreciated!

Yuntao


InnoVus Sroute IMPSR-2405

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Hi,

I am running sroute in Innovus ang get warning : (IMPSR-2405): Specified pin WIRECELL_EXT_CSF_FC_LIN ANAIO does not match db pin.

The power and ground nets are not correctly connected to pads, so I suspect this warning has something to do with it. How to correct this?

I am using INNOVUS v19.11

Also I have found a error report on this Innovus version: CCMPR02290918 sroute fails to connect some stripes to pad pins

Is there a workaround to this ?

Could this actually be the root cause to the warning?

BR. Sirpa

Guidelines for the Digital Implementation Forum

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In addition to the general Community Guidelines, please follow the guidelines given below.

Before posting a question

  • Make sure you have searched the documentation, the Cadence Community (use Search Community on the right hand side of this page), Cadence Online Support and even Google. In many cases somebody else may have already asked a similar question and an answer may be available.
  • Remember that this is a community forum - all members, including the Cadence folks, are responding voluntarily as a sideline to their daily work.
  • If you have an urgent question, or something that will need discussion of or access to sensitive information, you should log a case with Cadence Customer Support.
  • If you have an open case with customer support, please do not also post the same question in the forums.

When posting a question

  • Create your own thread. Do not post on the end of another person's thread, especially when it has been dormant for some time. It's better to create a new thread and reference the earlier thread.
  • Limit a thread to a single subject, and preferably to a single question or small number of very closely related questions. Doing so makes the threads easier to follow.
  • Please post in English, as this will make it much more likely you'll get a response from the community.
  • Try to ask specific and bounded questions. You are much more likely to get a response.
  • Make sure you include the relevant data in your question. Usually, the more accurate information, the better the community can help you. However, also try to be brief, as a long post is less likely to get read. Remember that whilst you are familiar with your problem, others may not be - so put yourself in the shoes of the person reading the question, and ask yourself if it would be possible to understand the question without any additional background information that only you have access to.
  • When asking a question about software, state clearly which tools you are using, and which version (ideally the sub-version) of the tools you are using. This information helps to ensure that you will get a more specific answer.
    • Tool versions can generally be obtained by executing "toolname -version" (e.g. innovus -version, genus -version, etc) in a terminal window.
    • Providing the full version number (e.g. Innovus v20.13-s083_1 ) would be much more helpful than simply stating that you are using "Cadence" or "Innovus".
  • If you are asking for help, describe what you have already tried. People are more likely to try to help those that are trying to help themselves.
  • Do not double post in more than one Community forum. Double posting only marks you as an annoyance, and does not help you in getting answers any faster. Post your request in one forum only. All double posts will be removed.
  • Do not attach copyrighted material to your posts unless you own the copyright. In other words, do not post data that is not yours to post (e.g. model files, technology data from a third-party foundry). Such data will be removed from the forum.
  • A picture is often worth a thousand words, but it's better to show text as a text file or included in the post (if not too long) as it's easier to search and for somebody to reproduce.
  • If you attach an example, please use standard archive formats such as tar  and zip. Do not use proprietary formats such as rar.
  • Acknowledge peoples responses to your posts and let them know how their suggestions worked out for you.
  • Write carefully and clearly. Do not use instant messaging short hand. Define the meaning of obscure terms and acronyms.

check point to point resistance for power and and analog nets

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HI,

I want to know is there any way In which I can check point to point resistance for analog/power nets

Please let me know if anyone knows about it.

Thanks

Japesh

power nets not connected to PAD M3

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Hello,

I am using sroute command

sroute -connect { blockPin padPin padRing corePin floatingStripe } -layerChangeRange { M1(1) LB(9) } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -padPinTarget { nearestTarget } -deleteExistingRoutes -allowJogging 1 -crossoverViaLayerRange { M1(1) LB(9) } -area { 1076.874 1428.067 1190.36 1216.186 } -nets { VDD_CORE GNDS_CORE } -allowLayerChange 1 -targetViaLayerRange { M1(1) LB(9) } 

To connect Power and ground nets VDD_CORE and GNDS_CORE to respective PADs

The PG pins in pads are in M3 layer ( metal 3)  .

When looking at the innovus GUI  I can not see the M3  layer in PADS and looks that the the nets are NOT connected.

How can I get them connected?

Innovus hold-time optimization in the presence of synchronizers

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Innovus somehow detects FF synchronizers in the circuit (which is good) and disables InPlaceOptimization of synchronizer nets. However, it seems that negative hold time slacks of non-optimized nodes prevent to meet the desired hold time slack in the rest of the circuit. My project is based on 180 nm technology and I target 0.2 ns hold time slack. In the presence of synchronizer nets with ~ -0.2 ns hold time slack, the best positive hold time slack after 'opt_design -post_route -setup -hold' is reported in the range of 0.03 ns.

Are there any suggestions how to implement circuits with synchronizers ?

Is there any way to exclude disabled nets from the optimization  ?

dusan.raic@fe.uni-lj.si

or

raic.dusan@gmail.com

Netclass and Netgroup in Innovus

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What exactly is the difference between Netclass and netgroup?

For example, if I give simple Netclass constraint in Innovus,  the command report_net_groups shows netclass constraint as output.  so, netClass is a kind of netgroup? what's the difference?

What is the meaning of "Cell Utlilization"?

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What is the meaning of Cell utilization and core utilization? PDF given in another forum with the same concept/question is bit confusing. What I understood is

Cell utilization = (Total number of cells that are present in the die) / ( Maximum number of cells that can be placed in the die) .


Core Utilization = (Total number of cells that are present in the core) / ( Maximum number of cells that can be placed in the core).

Is it right? Please correct me, if it isn't.

Thank you 


How to understand the nomenclature of dbGet commands?

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Hello everyone

A beginner here. I am trying to understand dbget commands. But it would really help me, if I could get a source which tells me how they have given the names to the commands. I'm not able to understand what are sWire, Hinsts, terms, etc. I see that the detailed explanation is not available in cadence text command reference website. So could you please tell how can I understand them ?

Thank you

[Innovus] How to relative place 2 standard cells abut?

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Hi all,

I have a placement requirement for the synchronizer flops that 2 flops of synchronizer block must be placed abut as below:

There are so many synchronizer blocks in my design so I cannot place the flops manually. 

Is there any way to tell INNOVUS to place the synchronizer flops as above pattern automatically (like ICC2 relative placement)?

Many thanks

"A mandatory condition failed to be true, Condition: Snz_Nets::sxNetsNet"-error when running "timeDesign" in Innovus

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Hello,

we are trying to route a custom 2-stage hierarchical design using Innovus using the following tool versions obtained by "innovus -version":

  • Innovus v20.11-s130_1 (64bit) 08/05/2020 15:53 (Linux 2.6.32-431.11.2.el6.x86_64)
  • NanoRoute 20.11-s130_1 NR200802-2257/20_11-UB (database version 18.20.512) {superthreading v2.9}
  • AAE 20.11-s008 (64bit) 08/05/2020 (Linux 2.6.32-431.11.2.el6.x86_64)
  • CTE 20.11-s059_1 () Aug  2 2020 05:46:30 ( )
  • SYNTECH 20.11-s028_1 () Aug  1 2020 06:14:27 ( )
  • CPE v20.11-s013
  • IQuantus/TQuantus 19.1.3-s260 (64bit) Thu May 28 10:57:28 PDT 2020 (Linux 2.6.32-431.11.2.el6.x86_64)
  • OA 22.60-s011 Tue Jun 16 12:27:00 2020
  • SGN 20.10-d001 (01-Jun-2020) (64 bit executable, Qt5.9.0)
  • RCDB 11.15.0
  • STYLUS 20.10-p011_1 (06/03/2020 04:47 PDT)

When Innovus is running "timeDesign -postRoute -prefix route" it aborts with the following error:

 83 ERROR (Cpp-2) :
 84 ----------------------   FATAL   ----------------------
 85 A mandatory condition failed to be true at line 1348 of file snzcaps.h.
 86 Condition: Snz_Nets::sxNetsNet()
 87 [SimplexCppLib::AssertFailureMsg]
 88 -------------------------------------------------------

I am having trouble to figure out what causes the error / understanding what the actual issue is since I am rather new to the field and the Cadence tool chain.
Did someone encounter a similar issue before, can clarify or maybe just point me to a more detailed error description? Much appreciated!

This is the generated log file (~5kB):

community.cadence.com/.../4401.extr.0.parallel_5F00_processing_5F00_0.log

news update times

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The news is always changing over the globe and is known as the world news. news update times This is one of an important reason why people should be up to date with all kinds of news.  There is an improvement in technology and people are viewing and reading news of all kinds.

Wreal Assign in for loop not working

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Hi,

I have the below statements when given outside the forloop it works but within the forloop it does not

genvar i;

real b;

wreal a;

generate
for (i=0; i<20; i=i+1) begin
assign a = b;
end
endgenerate

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