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Problem with adding block rings

June 7, 2021, 8:36 am
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I am making a chip with a single-sided padring (ie not a ring as pads are only on the bottom). I created the floorplan in Innovus, placed macros and added a core ring without any issues. However, when I try to add block rings around the macros I get this error:

**WARN: (IMPPP-4051): Fail to add rings. Gaps among IO cells may exist. Execute command addIoFiller to fill gaps among cells before addRing.

There are no gaps in the IOs and I have run the addIoFiller to make sure, and as expected no fillers are being added, but the error persists. Any idea what the problem might be?

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External Macro Placement and Constraining

June 10, 2021, 6:32 am
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For now we develop new project with number external hard macro devices (let's say it'll be few SPI modules, for simplification). Any of this external macro driven by generated clock in pretty similar frequency as main project. But main issue - we have analog-on-top flow and main digital pars is instantiated just as one of block in layout level.

I'm wandering is there some convenient method to manage timings/constraints for external macro (maybe some virtual macro connection). Basically we know exact timing relation for macros inputs/outputs and create it as library cell (with verilog, liberty and LEF) but obviously we cannot insert it to digital as it is not part of main digital part. Second problem - this macros will be moved and connection to them will be changed in different stages of layout so all the time we should need to recalculate input/output delay (with including numbers specified in liberty for macro).

In case there is exist some way to place this macro outside the boundary in innovus and count library numbers with some minor tuning of input/output delay - it would be great (without transfer this macros to layout).

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Library characterization using Cadence

June 16, 2021, 2:42 pm
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Hi,

I am trying to build a customized standard cell library using cadence. Right now, I met the problem to run the automatic library characterization. I searched online find there is an ELC tools. However, I can't find the ELC in my cadence directory. The packages on our server is ASSURA41, CONFRML161, EDI142,EXT152,IC617,INCISIVE152,INNOVUS162,MMSIM151,PVS161,VIPCAT113 and XCELIUM1704. I was expecting the ELC tools to be under EDI142 folder but couldn't fine it.

Can anyone help me with finding the ELC tools or any other possible way to run the library characterization.

Thank you very much,

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Query nets/cells causing DRVs using Tcl or dbGet commands to automate ECO flows

June 23, 2021, 2:03 pm
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Dear all,

I'm currently facing some issues with signoff timing closure for a highly congested block design.

In short,  the flow runs fine up to signoffTimeDesign in Innovus, however I'm not able to find an "automated" way to fix a few residual DRVs (max_tran and max_cap) in my design apart from invoking ECO flow commands such as ecoChangeCell or ecoAddRepeater"by hand" in interactive Innovus sessions according to reports generated using timeDesign, signoffTimeDesign, reportTranViolations or reportCapViolations commands.

I would like to know if there are flows that allows to "automate" a little bit these small fixes in such cases, mainly due to the fact that net names or cell instance names causing these few residual DRVs usually changes from run to run.

What I'm searching for is basically a Tcl flow that allows to:

1. identify nets or cells violating DRVs such as max_cap and max_tran using Tcl or dbGet commands

2. obtain a database pointer to these net/cell objects

3. automatically run ECO commands such as ecoChangeCell or ecoAddRepeater  targeting nets or cell names extracted from the database pointer

Just to be clear, I'm not asking how to generate DRVs reports or how to fix them using the default setOptMode/optDesign -drv flow, I would like to automate fixes for residual DRVs without the need of fixing them one after the other "by hand" using ECO commands interactively.

Any suggestion would be more than appreciated !

Cheers

Luca

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coonverting binary to decimal outout

June 26, 2021, 10:53 am
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Hı, I have 3 bit analog bits. I want to convert it to sıgned decimal output except 3'b100. because I want to get 3'b100 as a 0100(convert '-4' to '4'). Can u help me verilogA code for converting, please?

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Innovus connecting levelshifter power pin

June 28, 2021, 1:35 am
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Hi All,

I'm new to BE design and I'm now at the stage to place&route. I have levelshifters in my design with a VDD and VDDL pin. The VDD pin is shared with all other STD_CELLs so is connected by abutment. The VDDL pin needs to be routed to a different power domain. The pins/nets are listed in when I open POWER -> CONNECT GLOBAL NETS so the tools is aware of these connections. However if I run my current flow the pins are not connected. 

I did find the command "routePGPinUseSignalRoute" and this looked to solve my problem. However when I run this command all routing created during "placeDesign" is removed and when I run the next step in my script the new power connections are removed again.

Can anyone help me solve this issue, thanks.

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Should Run Post Route Again after DRC fix?

July 20, 2021, 8:38 am
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Hi,

after i run post-route in innovus, i want to verify my design using commands check_drc, delete_routes -regular_wire_with_drc, route_design. Then should i run again post route timing analysis and optimization?

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Power Analysis via Innovus

July 26, 2021, 4:24 am
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I faced two issues when I ran power analysis through Innovus.

Firstly,  according to"Basic" tab in "Run Power Analysis" window, the unit of Dominant Frequency is MHz, while it shows GHz during Static/Dynamic power analysis. For example, I put 10 in the "Dominant Frequency " blank space which i expected a frequency of 10MHz but during simulation it shows the frequency of 10GHz in console window.

Secondly, when I double the frequency  (let say changing from 10MHz to 20MHz), I expected the total switching power and internal power doubled (as explained in Innovus user guide, the switching power has a direct relation with frequency).
Actually by increasing the frequency the total switching power decreases!!
I am wondering if it is a bug of the power analysis in Innnovus or I have missed some set-up points during the analysis.

Thanks, Mehregan 

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[INNOVUS] failed to save holdtimer due to IO error (IMPOPT-7118)

August 3, 2021, 6:38 pm
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Hi all,

I got this error message (IMPOPT-7118) during hold fixing in optDesign -postCTS -setup -hold, then INNOVUS crash by internal ABORT signal. 

Can you help to solve this issue.

Thanks

Huy

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INNOVUS Placement regular structures

August 16, 2021, 1:10 am
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Hello

My current project have wide area and pretty big part of it are regular structures (like registers and some comb schematic) which duplicates about 512 times.

Which of way are more relevant and convenient to implement:

1. Use hierarchical flow, so I can create this regular structure independently and just put it as macro (something similar?). But I have no experience in this way and even don't know where to dig (some links will be preferable).

2. Use Structured Data Paths (SDP) from Innovus UG. As well I have no experience and don't know pros/cons regarding to previous way.

Thanks in advance for any comments and links to materials.

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[INNOVUS] Cannot import timing library files. IMPSYC-2

August 31, 2021, 10:07 am
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Greetings,

I have recently begun using Innovus to implement a digital circuit. I have a simple verilog design of a majority voter, and my goal is to walk each step the digital implementation process. The digital library I'm using is UMC 65nm. I successfully generated a synthesized design through Genus. Now I am trying to import the design in innovus, but I have encountered issues. Both the verilog netlist obtained from genus and the lef files provided by the foundry are imported without problems. However, when I try to import the timing library through the MMMC view file the following warning comes up:

IMPSYC-2: Timing information is not defined for cell MAO222M1RA; Check the timing library (.lib) file and make sure the timing information exists for the cell and you can run the checkTimingLibrary command to verify if the timing library has complete information after the design is loaded. Type 'man IMPSYC-2' for more detail.

And the following error:

IMPSYT-7007: clink executable was not found. 

The cell MAO222M1RA is a logic gate, and when I checked the timing library file it was there with all the appropiate delay information. I also tried using another library file with the ccs format and it didn't work either, as well as diferent verilog designs. The view file is very simple:

# Version:1.0 MMMC View Definition File
# Do Not Remove Above Line
create_library_set -name *name of the library* -timing {*file*}

I do not understand this issue since to me the library is well defined, and I don't understand what "clink executable was not found" means either. I was wondering if anyone could help me out, since I need the circuit delay but have been stuck here for some time. 

Thanks. 

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IMPESI-3490 Error in Tempus

September 8, 2021, 5:43 am
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Hi,

During ECO generation in Tempus I'm getting the following error on which Tempus exits. What is SMSC w.r.t below & how to set this?

**ERROR: (IMPESI-3490): cdB based analysis is not supported with CMMMC configuration. This may result in inaccurate analysis. Configure and run analysis in SMSC if using cdBs.

Regards,

Gautham

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Innovus write_netlist -phys with no POWER/GROUND INOUT in main module

October 3, 2021, 3:08 pm
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Hello all,

I am using Innovus for my physical synthesis.

I am writing the netlist with the command:  write_netlist -phys ../results/logic_control.v

My power/ground nets are DIGI_VDD and DIGI_GND. However, there is no power/ground input in the main module.

The logic gates connection with  DIGI_VDD and DIGI_GND nets are ok.

Is there a way to include the power/ground inputs in the main module? I am using Innovus v20.10.

Thanks in advance.

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[Voltus] Why static IR drop require timing window (TWF) file?

October 10, 2021, 10:04 pm
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Hello all, 

I got 2 questions about Voltus static power analysis.

1. Can you help to clarify below concept in Voltus UG:

It quite strange because switching power belong to dynamic power. 

2. Why static IR drop check require TWF file? I thought this file is used for dynamic vectorless IR drop check. 

Thank you,

Huy

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[GENUS] Different synthesis results using 19.11 or 19.14

October 24, 2021, 1:27 am
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Hi all!!

I am using genus to synthesize a digital design using the globalfoundries FDSOI 22 nm tech. I have updated the tool version from 19.11 to 19.14 and, using the same the script for the synthesis, the timing results have worsened. Now we are getting more than 100 ps "extra" negative slack (we had negative slack before but now it is even worst).

I guess it is a matter that some of the "default" values of the genus variables have changed,  my problem is that I don't know how to confirm it. Is there a way to know why the timing results are different? Is there a way to print out all the genus variables (like get_db * > variables.rpt)?

Thanks in advance

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voltus option power_enable_state_propagation?

October 27, 2021, 9:41 am
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Could I some information on voltus option power_enable_state_propagation? UserGuide has no meaningful definition of what this does exactly.

Thanks,

Kurt

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Innovus short ports with cds_thru block causing LVS error

November 10, 2021, 1:49 pm
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Hello,

I am trying to do PnR with Innovus and I faced an issue with the output layout where two output ports logic were reduced into being the same port, so Innovus decided to short them together by a cds_thru block between them. On running LVS, the layout gives short circuit errors between two different ports. My intention is to actually have to ports with the same signal output because I need to wire each from a different side of the layout (one from the left and the other from the right), I don't want to use a single port and manually route ~100um of wire to reach the other side of the digital layout. The fab will not accept non-clean LVS according to their rules, so I can't even waive these errors on my end.

My question is: Is there a way in Innovus to replace all cds_thru blocks to be buffers or metal resistance so that LVS can pass without an issue? 

I would appreciate any help on solving this issue, please.

Many thanks in advance!

Cadence tool versions:

- Virtuoso: sub-version IC6.1.8-64b.500.21

- Innovus: v21.11-s130_1 

Kindest Regards,

Nader Fathy

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How to route the 5th terminal of soi DeCap in innovus?

November 27, 2021, 7:33 pm
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Hi!

 

Our soi technology cells have the 5th terminal VBGP/VBGN, which means it should be connected for all VBGP and VBGN in innovus. However, the 5th terminal for DeCap would be ignored while routing because DeCap is treated like a FILLER with VDD and GND only. Is there any way to make innovus identify VBGP and VBGN for DeCap?

 

We have tried to keep DeCap pg pin only and short circuited pg pin and the 5th terminal (VBGP is connected with VDD and VBGN is connected with GND). Anyway, it failed to pass LVS verification. So could you please give me some advice? Thank you in advance!

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How to vary βn/βp ratio for a cmos inverter?

December 5, 2021, 10:03 am
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Hi,

I have built a cmos inverter (pmos2v and nmos2v) using cadence virtuoso. I need to vary the  βn/βp ratio and plot VTC for the same. can somebody tell me from where do i modify this factor. i am new to virtuoso, hence i will need a step by step guideline.

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Frozen Innovus GUI while executing Tcl script to highlight and zoom to wires

December 9, 2021, 4:47 am
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Hello,

I am trying to execute the following tcl script:

proc pause {{message "Hit Enter to continue ==> "}} {
puts -nonewline $message
flush stdout
gets stdin
}

set rh_rpt_dir {...}

set layers_names "..."

foreach l $layers_names {
setLayerPreference $l -isVisible 0
}

### SHORTS CHECK

append short_rpt $rh_rpt_dir "shorts.rpt"

set fid [open $short_rpt r]

while {![eof $fid]} {

gets $fid line

regexp -nocase -- {[0-9]+ +(\w+) +(\w+) +(\w+) +(\d+\.?\d*) +(\d+\.?\d*) +(\d+\.?\d*) +(\d+\.?\d*) +(\w+) +\w+ +(\w+)} \
$line all net1 net2 layer x1 y1 x2 y2 type1 type2

highlight -color red [dbGet -p2 [dbGet -p2 top.nets.sWires.net.name $net1 ].layer.name $layer]

highlight -color blue [dbGet -p2 [dbGet -p2 top.nets.sWires.net.name $net2 ].layer.name $layer]

setLayerPreference $layer -isVisible 1

zoomTo $x1 $y1 -radius 10

redraw

pause
}

close $fid

I used the pause procedure to see the changes in highlights and zoom, but the Innovus GUI is frozen and I cannot interact with it.

How can I solve this issue? Thank you

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