Hi,
I designed a 4x1 mux using 2x1 mux. This 2x1 mux was designed using nand gates as shown in the figure. I am unable to obtain required signal at the output of 4x1 mux. can somebody please tell me the reason for the same and how to rectify it.
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Weird signal at output of 4x1 mux
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Error while parsing Timer report file in Timing Report Validation Flow of Conformal Constraints designer
I am getting errors while trying to read timing report in Timing Report Validation Flow of Conformal Constraints designer, generated by Genus synthesizer.
Can anybody help me out with this issue.
Regards
Qazi Shahid Ullah
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warning: global net connections have not been applied to the instance!
Hi guys,
I used Innovus15 to do post route for my DSM, but when I export .v netlist after all procedures finished, I got these warnings:
<CMD> saveNetlist -includePowerGround ../postlayout/MASH_DSM_03.vWriting Netlist "../postlayout/MASH_DSM_03.v" ...Pwr name (VDD).Gnd name (VSS).1 Pwr names and 1 Gnd names.**WARN: (IMPVL-531): None of the instances inside cell/module 'accum_1_DW01_add_0' has power/ground connections, likely because global net connections (from globalNetConnect or CPF) have not been applied to the instances. Make sure this is acceptable, or apply the needed GNCs/CPF to make the required power/ground connections and re-save the netlist.Creating all pg connections for top cell (MASH_DSM).
Then I opened this .v file I found that the module 'accum_1_DW01_add_0' onlly defined input ports and output ports, there are nothing else:
module accum_1_DW01_add_0 ( A, B, CI, SUM, CO, p1); input [23:0] A; input [23:0] B; input CI; output [23:0] SUM; output CO; input p1;
// Internal wires wire n2; wire [23:1] carry;endmodule
But what unreasonable is I got two same module in .v ntelist after digital complier(the only difference between these two module is their name), the other one is correct while this one is not.
I don't know how to debug my errors, because clearly logs produced by Innovus didn't return any errors. And I tried several times, the result is always same. Could you give me any suggestions?
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Bluetooth 5.0 Transmitters
I'm curious if anyone has a 5.0 Bluetooth transmitter that they've paired with the Nox to determine if it's an APTX LL transmitter or not. I have three Taotronics TT-Ba07, 08, and 09 versions, however, none of them give the + sign when coupled with the machine. I'm not attempting to utilize it with the Nox, but rather with a different machine. When my Q-12 earbuds are linked, the Plus sign appears. I'm looking for a transmitter to utilize with the Q-12s that has the least amount of lag. Any suggestions or ideas would be much appreciated.
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Voltus extraction error
Hi All,
i have tried rail analysis on top level and while doing extraction is shows below error and flow is stoped
** ERROR: (VOLTUS_EXTR-1013): Unexpected condition has occurred. Terminating the program execution.
vector::_M_range_check: __n (which is 4294966193) >= this->size() (which is
1)
can anyone help me in this issue
Thanks in advance
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flowkit flowtool dist.py other grid useage namely SGE
Hi,
just wondered if others have moved over to using flowkit flowtool for script use.
Am going to try to use it for Tempus DMMMC.
Has anyone got an example of the dist.py for SGE (or other grid engine commands)?
As the python isn't the easiest to wade through.
ta,
Matt
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Diode inquiry
Pondering a build from the parts drawer. The enclosed found circuit utilizes a pair of 1N914 diodes. I have a pair of BYY31's. I've compared data sheets, but diodes are still a bit of a mystery to me. Would they allow the circuit to function? I'm not concerned with duplication... though still responding to CV would be critical. I'd be building it with mil-spec LM118's instead of TL082's as that's what I have.
I plan on breadboarding before drilling faceplate holes in stock. Any thoughts, or should I take the extra few days and order parts?
Text with the circuit claims 100Hz to 10kHz from a CV of .05 to 10 volts. I am utterly unconcerned with its linearity, simply that its frequency of oscillation alters substantially within that voltage range.
Thanks for any thoughts or advice!
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how can i get the same result of timing analysis from EDI and Tempus?
i did P&R by EDI tool and cleared all timing violations in the timing reports
but when i did sta by tempus, there's lots of hold violations by negative slacks
is this diffrence come from just by the tool engine performance ? or are there some methods or options that i can get the same timing analysis results from the edi?
SIAware setting is true
plaese help me
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[INNOVUS] Automatic Placement with Hierarchal "Top Down" design?
Hi,
Anyone know how to automatically place the module blocks for hierchal design?
I've tried to use the "proto_design" command but I get an error (IMPFM - 760) stating that "The design has no flexmodel, please specify planDesign seeds in a constraint file and do proto_design - constraints."
I can't figure out how to create a constraints file. Is there a way to automatically generate one with the GUI? Also, how to create a flexmodel for "planDesign"?
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[INNOVUS] Performing top level implementation for hierarchal/block IC design ("Bottom Up" approach)
I'm currently trying to perform the "bottom up" block design (hierarchal) approach in Innovus.
It is very challenging to understand how to implement the top-level module.
The User guide states the below:
"After block implementation, physical and timing abstract models (ILM/FlexILM) should be
developed for each block-level design that will be used in the top-level implementation. For the
bottom-up approach, create a top-level floorplan where block-level abstracts are referenced in the
top-level design."
Two questions:
1.) How to create ILM and FlexILM for a design?
2.) Anyone know what "top-level floorplan where block-level abstracts are referenced in the top-level design" means?
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Creating a LEF using Innovus
Hi,
Is there a link to cheatsheet or handy commands for the following purpose:
- If I know my pin IO and the layers they need to be in, is there a way to create a LEF using innovus? I feel a tcl based foreach will be easier for me to script and maintain as I am not familiar with Skill (to do it in Virtuoso XL). I don't have full layout yet to generate from my design.
- Ideally, I would like a cheatsheet or steps to say
a) I have innovus open. I would like to open a new design/blank canvas
b) create a bounding box for the block
c) create ports or pins and snap to nearest legal grid
d) save as LEF
Thank you in advance for the help.
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Liberate "define_leafcell" for a four terminal HBT
Hello All,
For context, I am trying to realize an ECL standard cell library via Liberate. In order to do this, I must define the HBT as a leafcell. An HBT is a subset of BJTs and as such would be characterized as an npn device, but the HBT models we are using have a fourth contact for the substrate. To this end, we expect the following line in our characterization tcl script:
define_leafcell -type npn -pin_position {0 1 2 3} { [HBT devices] }
This line will create a four terminal bjt style device, but instead of the substrate contact, we will have a second emitter. Are there any methods of doing this cleanly (maybe blackbox command)?
Thank you
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[INNOVUS] Pin assignment with hard macros
I am using innovus and I'm having problems with routing to the pins on my hardmacro.
Basically, since the pins are fixed, I can't re-do pin assignment to locate the pins in positions that are advantageous to PnR for my full design.
Is there any internal tool I can use for better pin assignment? I actually have the RTL for the hardmacro.
I am doing "bottom up" approach in which case I do PnR on leaf cells, export them as LEF files, then import as a larger design.
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Netlist Power Analysis Flow with RTL Stimulus
Hi all,
I am exploring Joules for the power analysis of a netlist synthesized with Genus. Eventually I want to plot the power activity of a stimulus along with the frames. The .vcd is parsed with the read_netlist command. Then, although a stim#1 is generated with various frames, when "compute_power -mode time_based" is executed it returns: "-time_based option is set for single frame SDB, : using average analysis", resulting in a single framed stimulus.
I suppose that my main proble here is to record the set of frames for the stimulus. In fact, when I do either "compute_power -mode time_based" or also "propagate_activity -mode time_based" the result is that the stimulus has only one frame, preventing the time_based mode to be executed (and therefore executing the average one). I extensively explored the lecture slides, labs, user manuals, command reference and the scripts provided along with the rapid adoption kits, but nothing seems to address such issue.
Here are the script steps to generate elaborated database:
- load technology files (libs, lefs, capt);
- read HDL files;
- elaborate design;
- add sdc constraints;
- write_db elab.db;
Script for power analysis from vcd:
- rtlstim2gate -init $ELAB_JDB -keep_libraries;
- read_netlist;
- read_sdc;
- read_stimulus -frame_count 10 -file dump.vcd;
- compute_power -mode time_based;
From the above script, what I would expect is a stimulus equally separated in 10 timeframe (/stim#1/frame#1/, /stim#1/frame#2/, ... /stim#1/frame#10/), but what I get instead is only /stim#1/frame#1/ and compute_power automatically switches to average mode, preventing me to plot the activity.
Any suggestion or indication is appreciated. Thank you.
Regards,
Dario
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Netlist Power Analysis Flow with RTL Stimulus
Hi all,
I am exploring Joules for the power analysis of a netlist synthesized with Genus. Eventually I want to plot the power activity of a stimulus along with the frames. The .vcd is parsed with the read_netlist command. Then, although a stim#1 is generated with various frames, when "compute_power -mode time_based" is executed it returns: "-time_based option is set for single frame SDB, : using average analysis", resulting in a single framed stimulus.
I suppose that my main proble here is to record the set of frames for the stimulus. In fact, when I do either "compute_power -mode time_based" or also "propagate_activity -mode time_based" the result is that the stimulus has only one frame, preventing the time_based mode to be executed (and therefore executing the average one). I extensively explored the lecture slides, labs, user manuals, command reference and the scripts provided along with the rapid adoption kits, but nothing seems to address such issue.
Here are the script steps to generate elaborated database:
- load technology files (libs, lefs, capt);
- read HDL files;
- elaborate design;
- add sdc constraints;
- write_db elab.db;
Script for power analysis from vcd:
- rtlstim2gate -init $ELAB_JDB -keep_libraries;
- read_netlist;
- read_sdc;
- read_stimulus -frame_count 10 -file dump.vcd;
- compute_power -mode time_based;
From the above script, what I would expect is a stimulus equally separated in 10 timeframe (/stim#1/frame#1/, /stim#1/frame#2/, ... /stim#1/frame#10/), but what I get instead is only /stim#1/frame#1/ and compute_power automatically switches to average mode, preventing me to plot the activity.
Any suggestion or indication is appreciated. Thank you.
Regards,
Dario
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MMMC cdB library in Voltus or Tempus 21.10
Hi,
I am using Innovus/Voltus/Tempus 21.10 but experiences a fatal error when loading the design finished by Innovus in Voltus or Tempus: (read_db -oa_lib_cell_view ; actually the first command in the init script )
**ERROR: (IMPESI-3490): cdB based analysis is not supported with CMMMC configuration. This may result in inaccurate analysis. Configure and run analysis in SMSC if using cdBs.
The tool self-closes.
The MMMC av definition includes library sets with -timing links to ecsm libraries as well as -si links to cdb libraries for signal integrity. The implementation flow with innovus runs succesfully but signoff tools complain about the cdb libraries. When I run implementation without cdb, it is loaded without errors in voltus/tempus.
Same issue with flowkit/flowtool when si_files are defined .
I'm using oa libraries throughout the entire flow. How should I load the oa library in voltus correctly and switch to SMSC? Or is the cdb based analysis deprecated?
Similar report here: https://community.cadence.com/cadence_technology_forums/f/digital-implementation/49165/impesi-3490-error-in-tempus
Thanks a lot!
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[Innovus] create_generated_clock giving strange error TA-152
Hello,
I'm using Innovus (v21.11-s130_1) to do PnR for a simple instance of a clock divider synthesized by genus shown below:
module GENERATE_CTRL_CLOCKS #(parameter CLK_DIV_FACTOR = 5) (CLK_FAST,RST,CLK_SLOW); input CLK_FAST; input RST; output reg CLK_SLOW; // Counters & aux clocks reg [CLK_DIV_FACTOR-1:0] clk_counter; wire [CLK_DIV_FACTOR-1:0] clk_counter_incr; // Generate Clock Division always @ (posedge CLK_FAST or negedge RST) begin if (!RST) begin clk_counter <= {(CLK_DIV_FACTOR){1'b0}}; end else begin clk_counter <= clk_counter_incr; end
end assign clk_counter_incr = clk_counter + { {CLK_DIV_FACTOR-1{1'b0}}, 1'b1 }; assign CLK_SLOW = ~clk_counter[CLK_DIV_FACTOR-1]; // Freq is CLK_DIV_FACTOR slower than fast clockendmodule
module MAIN (CLK_FAST,RST); input CLK_FAST; input RST; wire CLK_SLOW; // Call clock div: GENERATE_CTRL_CLOCKS #(.CLK_DIV_FACTOR(5)) generate_ic_clocks(.CLK_FAST(CLK_FAST),.RST(RST), .CLK_SLOW(CLK_SLOW));endmodule
My SDC to generate the clocks are defined as:
- create_clock [get_ports CLK_FAST] -name clkf -period 48
- create_generated_clock -name clks -source [get_ports CLK_FAST] -divide_by 32 [get_pins generate_ic_clocks/CLK_SLOW_reg/Q]
Innovus gave me these errors when I do placeDesign:
- **ERROR: (TA-152): A latency path from the 'Rise' edge of the master clock at source pin 'CLK_FAST' to the 'Rise' edge of generated clock 'clks' at pin 'generate_ic_clocks/CLK_SLOW_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'clks'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
- **ERROR: (TA-152): A latency path from the 'Rise' edge of the master clock at source pin 'CLK_FAST' to the 'Fall' edge of generated clock 'clks' at pin 'generate_ic_clocks/CLK_SLOW_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'clks'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
I have viewed the article (https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nUuREAU&pageName=ArticleContent) that talks about this issue but my clocks don't have any of the mentioned issue.
If I flattened the module GENERATE_CTRL_CLOCKS on the main module and modified the path of SDC SLOW_CLK to [get_pins CLK_SLOW], Innovus recognizes the slow clock.
I'd appreciate it if anyone could help me understand why is this happening? and how do I fix this issue, please?
Nader Fathy
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[Innovus] report the fanout of ICG
I am looking for one way to report the ICG fanout status, below pic is the example of the ICG connection
I could get the fanout count of ICG a :
> sizeof_collection [all_fanout -from a -endpoints_only] , then I will get 100+200+300+3(b,c,d)
Now, I want to get the regs count from a: 100; and b's fanout of regs: 200 and c's fanout of regs :300 respectively.
Any comments will be appreciated
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set_db cts_clustering_source_group_max_cloned_fraction 0.2
Where could I get more introduction about the command "set_db cts_clustering_source_group_max_cloned_fraction 0.2" ?
Any thread will be appreciate
Thanks
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set dont use
Hi experts
Is there a way to set dont use for special path_groups?
Thanks
Hammer
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