When I saveNetlsit in my innovus , I found Some PG nets which connected to std cell PG pins have been renamed ,  from VDD to VDD_UPF_IS_1, in netlist it shows like:

.VSS (VSS_UPF_IS_1)

.VDD(VDD_UPF_IS_1)

it should be 

.VSS (VSS)

.VDD(VDD)

I don't know the reason,  Does My UPF  conflict with my database Globalconnect ? 

Thanks

Hello,

Task: Floor Plan

Issue: Horizontal Power stripes are not interleaved or connected correctly.

Tool Version : Innovus 211

Tool Command: innovus -stylus

I am implementing the floorplan.  The Power Ring and Power stripes look correct, but when I run the route_special command with the intent of connecting the power and ground of the standard cells, the horizontal power rails are only VDD, there are no VSS rails.  The VDD and VSS of the standard cells can be seen, but he VDD route tramples over all VSS connections.

I don't know if I am missing an input file or if I have missed a step or setup option.  Any advice will be greatly appreciated.  The details of the command I ran and the log file output are listed below.

Thank you.
Regards,

Shane

The command I used is:

route_special \

    -connect {block_pin pad_pin pad_ring core_pin floating_stripe} \

    -layer_change_range { M1(1) M5(11) } \

    -block_pin_target {nearest_target} \

    -pad_pin_port_connect {all_port one_geom} \

    -pad_pin_target {nearest_target} \

    -core_pin_target {first_after_row_end} \

    -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} \

    -allow_jogging 1 \

    -crossover_via_layer_range { M1(1) M5(11) } \

    -nets { VDD VSS } \

    -allow_layer_change 1 \

    -block_pin use_lef \

    -target_via_layer_range { M1(1) M5(11) }

The log file for this command says:

route_special \

    -connect {block_pin pad_pin pad_ring core_pin floating_stripe} \

    -layer_change_range { M1(1) M5(11) } \

    -block_pin_target {nearest_target} \

    -pad_pin_port_connect {all_port one_geom} \

    -pad_pin_target {nearest_target} \

    -core_pin_target {first_after_row_end} \

    -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} \

    -allow_jogging 1 \

    -crossover_via_layer_range { M1(1) M5(11) } \

    -nets { VDD VSS } \

    -allow_layer_change 1 \

    -block_pin use_lef \

    -target_via_layer_range { M1(1) M5(11) }

#% Begin route_special (date=06/27 15:18:29, mem=1557.2M)

*** Begin SPECIAL ROUTE on Mon Jun 27 15:18:29 2022 ***

SPECIAL ROUTE ran on directory: *****

SPECIAL ROUTE ran on machine: file (*****)

Begin option processing ...

srouteConnectPowerBump set to false

routeSelectNet set to "VDD VSS"

routeSpecial set to true

srouteBlockPin set to "useLef"

srouteBottomLayerLimit set to 1

srouteBottomTargetLayerLimit set to 1

srouteConnectConverterPin set to false

srouteCrossoverViaBottomLayer set to 1

srouteCrossoverViaTopLayer set to 11

srouteFloatingStripeTarget set to "blockring padring ring stripe ringpin blockpin followpin"

srouteFollowCorePinEnd set to 3

srouteJogControl set to "preferWithChanges differentLayer"

srouteNoViaOnWireShape set to "padring ring stripe blockring blockpin coverpin blockwire corewire followpin iowire"

sroutePadPinAllPorts set to true

sroutePreserveExistingRoutes set to true

srouteRoutePowerBarPortOnBothDir set to true

srouteStopBlockPin set to "nearestTarget"

srouteTopLayerLimit set to 11

srouteTopTargetLayerLimit set to 11

End option processing: cpu: 0:00:00, real: 0:00:00, peak: 49.00 megs.

Reading DB technology information...

Finished reading DB technology information.

Reading floorplan and netlist information...

Finished reading floorplan and netlist information.

**WARN: (IMPSR-4302): Cap-table/qrcTechFile is found in the design, so the same information from the technology file will be ignored.

Read in 23 layers, 11 routing layers, 1 overlap layer

Read in 959 macros, 49 used

Read in 48 components

  48 core components: 48 unplaced, 0 placed, 0 fixed

Read in 2053 physical pins

  2053 physical pins: 0 unplaced, 2053 placed, 0 fixed

Read in 3 logical pins

Read in 2056 nets

Read in 2 special nets, 2 routed

Read in 2149 terminals

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the up vias on single M1 layer. The excess vias will be ignored.

**WARN: (IMPSR-4305): Reached the limit of the 128 candidates for the down vias on single M2 layer. The excess vias will be ignored.

**WARN: (EMS-27):     Message (IMPSR-4305) has exceeded the current message display limit of 20.

To increase the message display limit, refer to the product command reference manual.

2 nets selected.

Begin power routing ...

**WARN: (IMPSR-1254): Unable to connect the specified objects, since block pins of the VDD net were not found in the design. Check netlist or change the parameter value to include block pins in the design.

**WARN: (IMPSR-1256): Unable to find any CORE class pad pin of the VDD net due to unavailability of the pin or check netlist in the routing area or layer. Change routing area or layer to include the expected pin or check netlist. Alternatively, change port class in the technology file.

Type 'man IMPSR-1256' for more detail.

Cannot find any AREAIO class pad pin of net VDD. Check net list, or change port class in the technology file, or change option to include pin in given range.

**WARN: (IMPSR-1254): Unable to connect the specified objects, since block pins of the VSS net were not found in the design. Check netlist or change the parameter value to include block pins in the design.

**WARN: (IMPSR-1256): Unable to find any CORE class pad pin of the VSS net due to unavailability of the pin or check netlist in the routing area or layer. Change routing area or layer to include the expected pin or check netlist. Alternatively, change port class in the technology file.

Type 'man IMPSR-1256' for more detail.

Cannot find any AREAIO class pad pin of net VSS. Check net list, or change port class in the technology file, or change option to include pin in given range.

CPU time for VDD FollowPin 0 seconds

CPU time for VSS FollowPin 0 seconds

  Number of IO ports routed: 0

  Number of Block ports routed: 0

  Number of Stripe ports routed: 0

  Number of Core ports routed: 408

  Number of Pad ports routed: 0

  Number of Power Bump ports routed: 0

  Number of Followpin connections: 204

End power routing: cpu: 0:00:01, real: 0:00:02, peak: 50.00 megs.

Begin updating DB with routing results ...

Updating DB with 2053 io pins ...

Updating DB with 0 via definition ...Extracting standard cell pins and blockage ......

Pin and blockage extraction finished

route_special created 614 wires.

ViaGen created 2654 vias, deleted 0 via to avoid violation.

+--------+----------------+----------------+

|  Layer |     Created    |     Deleted    |

+--------+----------------+----------------+

|   M1   |       612      |       NA       |

|   V1   |       408      |        0       |

|   M2   |        2       |       NA       |

|   V2   |       408      |        0       |

|   M3   |       408      |        0       |

|   V3   |       408      |        0       |

|   M4   |       408      |        0       |

|   V4   |       408      |        0       |

|   M5   |       206      |        0       |

+--------+----------------+----------------+

#% End route_special (date=06/27 15:18:31, total cpu=0:00:01.4, real=0:00:02.0, peak res=1567.4M, current mem=1567.4M)

Hi,

How to add the wire length inside innovus  timing report as genus do ?

The timing_report_field is only having instance_loacation or pin_location option but not the wire_length.

Thanks, Cyrille.

Hello all,

I have two digital modules created in Cadence DC tool. When I import them to Virtuoso (as Verilog files) they have no VDD and GND pins. In this case i use VDD! and GND! as the power and ground rails for simulation.

However, I would like to separate the power nets - one module will be fed from DC rail V1 and the second from power rail V2 (each module has it own power nets which are not connected).

For that I need to create power and ground pins for each digital module. 

How can do this? Other suggestion are most welcomed. 

Thanks!

Hi guys

How to Can I Keep specific Net Wires Spacing out with other net wires in innovus ？

Introduction: Task at Hand

• Determine resonance frequencies of a chip + package model. Package model is available, models need to be created for the impedance introduced by power domains between the supplies.
• The chip is a large mixed-signal system in a 40 nm process with multiple power domains.
• Voltus has been used to generate PowerGrid Views. The tool can be used to generate reports for the library cells and in particular the "stdcells.report" which lists capacitance values extracted from simulations at cell level.
• Statistics are available about the number of cells used per domain, about supply rail lengths, etc.
• The intention is to compute totals of capacitances per domain, and deduce an average capacitance density per unit length of rail (as well as an associated series resistance to have correct rise-times). Then evaluate rails parasitics (series resistance and inductance, substrate resistance) and construct a distributed model using the averaged parameters for each domain.

Problem Description

• So far no precise definition was found in the various Voltus manuals for the capacitance values reported in the "stdcells.report".
• What is "grid capacitance" exactly ?
• What is "intrinsic capacitance" exactly ?

Questions

1. How can I determine what the precise definition is of the capacitances reported in the "stdcells.report" generated from the PG views ?
   Is there a way to look at the nelists used for extraction ?
   
   
2. It appears the "stdcells.report" lists one capacitance value per supply pin:  is this a capacitance computed with all other supply pins "AC grounded" or equivalently driven by a perfect voltage source ?
   
   
3. The capacitance values in the "stdcells.report" are independent of the logic level imposed on the inputs. However the capacitances to any supply from a given cell will depend how an external driver ties a particular input of the cell to any of those supplies...  So what is then the value reported in the  "stdcells.report" ? Is is assuming some distribution of logic levels at the inputs (eg assuming all possible combinations have the same probability) ?

Looking forward for hints on how find answers to these questions (or even better direct answers if possible) !

I am designing an inverter and wanted to to do the corner simulation. From the documents I came to know about correlated corners. These are common Fet and common Feol. I see both corners are needed to successfully run the simulations and I get 25 corners instead of only  5. Your guidance would be highly appreciated.

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It happened that i use two versions of Genus tool - 15.2 and 20.1 (mostly). The problem is - im sysnthesizing my project by use of .tcl-script and in 20.1 it completed well, but in the 15.2 after syn_map the tool had given me an error about wrong netlist. So it can't done my design properly and i can't use it in Innovus to implement my design eather.

Error is:

IMPVL-387 - illegal bus-bit reference. BLOCK.Name [X] [Y1] to scalar net BLOCK.Name [X]

IMPVL-387 - illegal bus-bit reference. BLOCK.Name [X] [Y2] to scalar net BLOCK.Name [X]

...

IMPVL-387 - illegal bus-bit reference. BLOCK.Name [X] [Yx] to scalar net BLOCK.Name [X]

I tried to find the description of this issue, but never succeeded.

I actualy never use versions under 19 of Cadence IC... Maybe someone of you know this error type and how to fix it (by fixing my script maybe for compatibility with 15.2. I've found that report_module - report module in this version, working on it)

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I am looking for adding delay buf at hold endpoints ,trying to trace out common point,so that i can put a buf at that point to see changes across all violating endpoints,I am stuck at the point ,to get the common point for example 1000 unique endpoints,please share your thoughts on how to approach.

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I'm using INNOVUS20.17 to P&R on .13 SiGe BiCMOS technology. The tech lib are converted from LEF file to OA with the lef2oa command. When I'm doing the power planning, the sroute command gives me some error message and leave all the power pins unconnected. It seems that the DB technology information is not properly loaded. How can I debug it? Thanks.

sroute -connect {padPin} -allowJogging 0 -allowLayerChange 0

Begin option processing ...
srouteConnectPowerBump set to false
routeSpecial set to true
srouteConnectBlockPin set to false
srouteConnectConverterPin set to false
srouteConnectCorePin set to false
srouteConnectStripe set to false
srouteFollowCorePinEnd set to 3
srouteFollowPadPin set to false
srouteNoLayerChangeRoute set to true
sroutePadPinAllPorts set to true
sroutePreserveExistingRoutes set to true
srouteRoutePowerBarPortOnBothDir set to true
srouteStraightConnections set to "straightWithDrcClean"
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 3321.00 megs.

Reading DB technology information...
   *ERROR* LAYER Metal2 is not a CUT LAYER
   *ERROR* LAYER Metal1 is not a CUT LAYER
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
   A total of 2 errors.

Hello,

I have a question about logic synthesis reports. As the dynamic power depends on the clock frequency, what is the power report of the cadence genus (report_power) when we synthesize a fully combinational logic without any clock?

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I'm curious as to the use cases of IEEE1500 (ECT) and IEEE1687 (IJTAG).

From what I understand you can have a IEEE1500 Wrapper that is IEEE1687 compliant, but I've been seeing that IEEE1500 is typically for "complex" cores (which I would assume to be on the lines of a microprocessor).

Does this imply that for non-complex devices only IEEE1687 is used? (I do understand that typically 1500 and 1687 would be paired with 1149.1) and if so what tools exist for inserting a 1687 TDR? I know that Genus allows you to insert a 1500 WIR. Is there a cadence tool that allows you to insert a 1687 TDR?

Apologies in advance if my nomenclature is off, I'm fairly new to the world of DFT.

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set_global _enable_mmmc_by_default_flow $CTE::mmmc_default
suppressMessage ENCEXT-2799
win

Can anyone explain me importance of the those commands,